1/*
| 1/*
|
2 * Copyright (c) 2012 ARM Limited
| 2 * Copyright (c) 2012, 2014 ARM Limited
|
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_O3_DECODE_IMPL_HH__
44#define __CPU_O3_DECODE_IMPL_HH__
45
46#include "arch/types.hh"
47#include "base/trace.hh"
48#include "config/the_isa.hh"
49#include "cpu/o3/decode.hh"
50#include "cpu/inst_seq.hh"
51#include "debug/Activity.hh"
52#include "debug/Decode.hh"
53#include "debug/O3PipeView.hh"
54#include "params/DerivO3CPU.hh"
55#include "sim/full_system.hh"
56
57// clang complains about std::set being overloaded with Packet::set if
58// we open up the entire namespace std
59using std::list;
60
61template<class Impl>
62DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params)
63 : cpu(_cpu),
64 renameToDecodeDelay(params->renameToDecodeDelay),
65 iewToDecodeDelay(params->iewToDecodeDelay),
66 commitToDecodeDelay(params->commitToDecodeDelay),
67 fetchToDecodeDelay(params->fetchToDecodeDelay),
68 decodeWidth(params->decodeWidth),
69 numThreads(params->numThreads)
70{
71 if (decodeWidth > Impl::MaxWidth)
72 fatal("decodeWidth (%d) is larger than compiled limit (%d),\n"
73 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
74 decodeWidth, static_cast<int>(Impl::MaxWidth));
75
76 // @todo: Make into a parameter
77 skidBufferMax = (fetchToDecodeDelay + 1) * params->fetchWidth;
78}
79
80template<class Impl>
81void
82DefaultDecode<Impl>::startupStage()
83{
84 resetStage();
85}
86
87template<class Impl>
88void
89DefaultDecode<Impl>::resetStage()
90{
91 _status = Inactive;
92
93 // Setup status, make sure stall signals are clear.
94 for (ThreadID tid = 0; tid < numThreads; ++tid) {
95 decodeStatus[tid] = Idle;
96
97 stalls[tid].rename = false;
| 3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_O3_DECODE_IMPL_HH__
44#define __CPU_O3_DECODE_IMPL_HH__
45
46#include "arch/types.hh"
47#include "base/trace.hh"
48#include "config/the_isa.hh"
49#include "cpu/o3/decode.hh"
50#include "cpu/inst_seq.hh"
51#include "debug/Activity.hh"
52#include "debug/Decode.hh"
53#include "debug/O3PipeView.hh"
54#include "params/DerivO3CPU.hh"
55#include "sim/full_system.hh"
56
57// clang complains about std::set being overloaded with Packet::set if
58// we open up the entire namespace std
59using std::list;
60
61template<class Impl>
62DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params)
63 : cpu(_cpu),
64 renameToDecodeDelay(params->renameToDecodeDelay),
65 iewToDecodeDelay(params->iewToDecodeDelay),
66 commitToDecodeDelay(params->commitToDecodeDelay),
67 fetchToDecodeDelay(params->fetchToDecodeDelay),
68 decodeWidth(params->decodeWidth),
69 numThreads(params->numThreads)
70{
71 if (decodeWidth > Impl::MaxWidth)
72 fatal("decodeWidth (%d) is larger than compiled limit (%d),\n"
73 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
74 decodeWidth, static_cast<int>(Impl::MaxWidth));
75
76 // @todo: Make into a parameter
77 skidBufferMax = (fetchToDecodeDelay + 1) * params->fetchWidth;
78}
79
80template<class Impl>
81void
82DefaultDecode<Impl>::startupStage()
83{
84 resetStage();
85}
86
87template<class Impl>
88void
89DefaultDecode<Impl>::resetStage()
90{
91 _status = Inactive;
92
93 // Setup status, make sure stall signals are clear.
94 for (ThreadID tid = 0; tid < numThreads; ++tid) {
95 decodeStatus[tid] = Idle;
96
97 stalls[tid].rename = false;
|
98 stalls[tid].iew = false;
99 stalls[tid].commit = false;
| |
100 }
101}
102
103template <class Impl>
104std::string
105DefaultDecode<Impl>::name() const
106{
107 return cpu->name() + ".decode";
108}
109
110template <class Impl>
111void
112DefaultDecode<Impl>::regStats()
113{
114 decodeIdleCycles
115 .name(name() + ".IdleCycles")
116 .desc("Number of cycles decode is idle")
117 .prereq(decodeIdleCycles);
118 decodeBlockedCycles
119 .name(name() + ".BlockedCycles")
120 .desc("Number of cycles decode is blocked")
121 .prereq(decodeBlockedCycles);
122 decodeRunCycles
123 .name(name() + ".RunCycles")
124 .desc("Number of cycles decode is running")
125 .prereq(decodeRunCycles);
126 decodeUnblockCycles
127 .name(name() + ".UnblockCycles")
128 .desc("Number of cycles decode is unblocking")
129 .prereq(decodeUnblockCycles);
130 decodeSquashCycles
131 .name(name() + ".SquashCycles")
132 .desc("Number of cycles decode is squashing")
133 .prereq(decodeSquashCycles);
134 decodeBranchResolved
135 .name(name() + ".BranchResolved")
136 .desc("Number of times decode resolved a branch")
137 .prereq(decodeBranchResolved);
138 decodeBranchMispred
139 .name(name() + ".BranchMispred")
140 .desc("Number of times decode detected a branch misprediction")
141 .prereq(decodeBranchMispred);
142 decodeControlMispred
143 .name(name() + ".ControlMispred")
144 .desc("Number of times decode detected an instruction incorrectly"
145 " predicted as a control")
146 .prereq(decodeControlMispred);
147 decodeDecodedInsts
148 .name(name() + ".DecodedInsts")
149 .desc("Number of instructions handled by decode")
150 .prereq(decodeDecodedInsts);
151 decodeSquashedInsts
152 .name(name() + ".SquashedInsts")
153 .desc("Number of squashed instructions handled by decode")
154 .prereq(decodeSquashedInsts);
155}
156
157template<class Impl>
158void
159DefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
160{
161 timeBuffer = tb_ptr;
162
163 // Setup wire to write information back to fetch.
164 toFetch = timeBuffer->getWire(0);
165
166 // Create wires to get information from proper places in time buffer.
167 fromRename = timeBuffer->getWire(-renameToDecodeDelay);
168 fromIEW = timeBuffer->getWire(-iewToDecodeDelay);
169 fromCommit = timeBuffer->getWire(-commitToDecodeDelay);
170}
171
172template<class Impl>
173void
174DefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
175{
176 decodeQueue = dq_ptr;
177
178 // Setup wire to write information to proper place in decode queue.
179 toRename = decodeQueue->getWire(0);
180}
181
182template<class Impl>
183void
184DefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
185{
186 fetchQueue = fq_ptr;
187
188 // Setup wire to read information from fetch queue.
189 fromFetch = fetchQueue->getWire(-fetchToDecodeDelay);
190}
191
192template<class Impl>
193void
194DefaultDecode<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr)
195{
196 activeThreads = at_ptr;
197}
198
199template <class Impl>
200void
201DefaultDecode<Impl>::drainSanityCheck() const
202{
203 for (ThreadID tid = 0; tid < numThreads; ++tid) {
204 assert(insts[tid].empty());
205 assert(skidBuffer[tid].empty());
206 }
207}
208
| 98 }
99}
100
101template <class Impl>
102std::string
103DefaultDecode<Impl>::name() const
104{
105 return cpu->name() + ".decode";
106}
107
108template <class Impl>
109void
110DefaultDecode<Impl>::regStats()
111{
112 decodeIdleCycles
113 .name(name() + ".IdleCycles")
114 .desc("Number of cycles decode is idle")
115 .prereq(decodeIdleCycles);
116 decodeBlockedCycles
117 .name(name() + ".BlockedCycles")
118 .desc("Number of cycles decode is blocked")
119 .prereq(decodeBlockedCycles);
120 decodeRunCycles
121 .name(name() + ".RunCycles")
122 .desc("Number of cycles decode is running")
123 .prereq(decodeRunCycles);
124 decodeUnblockCycles
125 .name(name() + ".UnblockCycles")
126 .desc("Number of cycles decode is unblocking")
127 .prereq(decodeUnblockCycles);
128 decodeSquashCycles
129 .name(name() + ".SquashCycles")
130 .desc("Number of cycles decode is squashing")
131 .prereq(decodeSquashCycles);
132 decodeBranchResolved
133 .name(name() + ".BranchResolved")
134 .desc("Number of times decode resolved a branch")
135 .prereq(decodeBranchResolved);
136 decodeBranchMispred
137 .name(name() + ".BranchMispred")
138 .desc("Number of times decode detected a branch misprediction")
139 .prereq(decodeBranchMispred);
140 decodeControlMispred
141 .name(name() + ".ControlMispred")
142 .desc("Number of times decode detected an instruction incorrectly"
143 " predicted as a control")
144 .prereq(decodeControlMispred);
145 decodeDecodedInsts
146 .name(name() + ".DecodedInsts")
147 .desc("Number of instructions handled by decode")
148 .prereq(decodeDecodedInsts);
149 decodeSquashedInsts
150 .name(name() + ".SquashedInsts")
151 .desc("Number of squashed instructions handled by decode")
152 .prereq(decodeSquashedInsts);
153}
154
155template<class Impl>
156void
157DefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
158{
159 timeBuffer = tb_ptr;
160
161 // Setup wire to write information back to fetch.
162 toFetch = timeBuffer->getWire(0);
163
164 // Create wires to get information from proper places in time buffer.
165 fromRename = timeBuffer->getWire(-renameToDecodeDelay);
166 fromIEW = timeBuffer->getWire(-iewToDecodeDelay);
167 fromCommit = timeBuffer->getWire(-commitToDecodeDelay);
168}
169
170template<class Impl>
171void
172DefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
173{
174 decodeQueue = dq_ptr;
175
176 // Setup wire to write information to proper place in decode queue.
177 toRename = decodeQueue->getWire(0);
178}
179
180template<class Impl>
181void
182DefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
183{
184 fetchQueue = fq_ptr;
185
186 // Setup wire to read information from fetch queue.
187 fromFetch = fetchQueue->getWire(-fetchToDecodeDelay);
188}
189
190template<class Impl>
191void
192DefaultDecode<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr)
193{
194 activeThreads = at_ptr;
195}
196
197template <class Impl>
198void
199DefaultDecode<Impl>::drainSanityCheck() const
200{
201 for (ThreadID tid = 0; tid < numThreads; ++tid) {
202 assert(insts[tid].empty());
203 assert(skidBuffer[tid].empty());
204 }
205}
206
|
| 207template <class Impl>
208bool
209DefaultDecode<Impl>::isDrained() const
210{
211 for (ThreadID tid = 0; tid < numThreads; ++tid) {
212 if (!insts[tid].empty() || !skidBuffer[tid].empty())
213 return false;
214 }
215 return true;
216}
217
|
209template<class Impl>
210bool
211DefaultDecode<Impl>::checkStall(ThreadID tid) const
212{
213 bool ret_val = false;
214
215 if (stalls[tid].rename) {
216 DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid);
217 ret_val = true;
| 218template<class Impl>
219bool
220DefaultDecode<Impl>::checkStall(ThreadID tid) const
221{
222 bool ret_val = false;
223
224 if (stalls[tid].rename) {
225 DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid);
226 ret_val = true;
|
218 } else if (stalls[tid].iew) {
219 DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid);
220 ret_val = true;
221 } else if (stalls[tid].commit) {
222 DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid);
223 ret_val = true;
| |
224 }
225
226 return ret_val;
227}
228
229template<class Impl>
230inline bool
231DefaultDecode<Impl>::fetchInstsValid()
232{
233 return fromFetch->size > 0;
234}
235
236template<class Impl>
237bool
238DefaultDecode<Impl>::block(ThreadID tid)
239{
240 DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid);
241
242 // Add the current inputs to the skid buffer so they can be
243 // reprocessed when this stage unblocks.
244 skidInsert(tid);
245
246 // If the decode status is blocked or unblocking then decode has not yet
247 // signalled fetch to unblock. In that case, there is no need to tell
248 // fetch to block.
249 if (decodeStatus[tid] != Blocked) {
250 // Set the status to Blocked.
251 decodeStatus[tid] = Blocked;
252
253 if (toFetch->decodeUnblock[tid]) {
254 toFetch->decodeUnblock[tid] = false;
255 } else {
256 toFetch->decodeBlock[tid] = true;
257 wroteToTimeBuffer = true;
258 }
259
260 return true;
261 }
262
263 return false;
264}
265
266template<class Impl>
267bool
268DefaultDecode<Impl>::unblock(ThreadID tid)
269{
270 // Decode is done unblocking only if the skid buffer is empty.
271 if (skidBuffer[tid].empty()) {
272 DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid);
273 toFetch->decodeUnblock[tid] = true;
274 wroteToTimeBuffer = true;
275
276 decodeStatus[tid] = Running;
277 return true;
278 }
279
280 DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid);
281
282 return false;
283}
284
285template<class Impl>
286void
287DefaultDecode<Impl>::squash(DynInstPtr &inst, ThreadID tid)
288{
289 DPRINTF(Decode, "[tid:%i]: [sn:%i] Squashing due to incorrect branch "
290 "prediction detected at decode.\n", tid, inst->seqNum);
291
292 // Send back mispredict information.
293 toFetch->decodeInfo[tid].branchMispredict = true;
294 toFetch->decodeInfo[tid].predIncorrect = true;
295 toFetch->decodeInfo[tid].mispredictInst = inst;
296 toFetch->decodeInfo[tid].squash = true;
297 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
298 toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
299 toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching();
300 toFetch->decodeInfo[tid].squashInst = inst;
301 if (toFetch->decodeInfo[tid].mispredictInst->isUncondCtrl()) {
302 toFetch->decodeInfo[tid].branchTaken = true;
303 }
304
305 InstSeqNum squash_seq_num = inst->seqNum;
306
307 // Might have to tell fetch to unblock.
308 if (decodeStatus[tid] == Blocked ||
309 decodeStatus[tid] == Unblocking) {
310 toFetch->decodeUnblock[tid] = 1;
311 }
312
313 // Set status to squashing.
314 decodeStatus[tid] = Squashing;
315
316 for (int i=0; i<fromFetch->size; i++) {
317 if (fromFetch->insts[i]->threadNumber == tid &&
318 fromFetch->insts[i]->seqNum > squash_seq_num) {
319 fromFetch->insts[i]->setSquashed();
320 }
321 }
322
323 // Clear the instruction list and skid buffer in case they have any
324 // insts in them.
325 while (!insts[tid].empty()) {
326 insts[tid].pop();
327 }
328
329 while (!skidBuffer[tid].empty()) {
330 skidBuffer[tid].pop();
331 }
332
333 // Squash instructions up until this one
334 cpu->removeInstsUntil(squash_seq_num, tid);
335}
336
337template<class Impl>
338unsigned
339DefaultDecode<Impl>::squash(ThreadID tid)
340{
341 DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid);
342
343 if (decodeStatus[tid] == Blocked ||
344 decodeStatus[tid] == Unblocking) {
345 if (FullSystem) {
346 toFetch->decodeUnblock[tid] = 1;
347 } else {
348 // In syscall emulation, we can have both a block and a squash due
349 // to a syscall in the same cycle. This would cause both signals
350 // to be high. This shouldn't happen in full system.
351 // @todo: Determine if this still happens.
352 if (toFetch->decodeBlock[tid])
353 toFetch->decodeBlock[tid] = 0;
354 else
355 toFetch->decodeUnblock[tid] = 1;
356 }
357 }
358
359 // Set status to squashing.
360 decodeStatus[tid] = Squashing;
361
362 // Go through incoming instructions from fetch and squash them.
363 unsigned squash_count = 0;
364
365 for (int i=0; i<fromFetch->size; i++) {
366 if (fromFetch->insts[i]->threadNumber == tid) {
367 fromFetch->insts[i]->setSquashed();
368 squash_count++;
369 }
370 }
371
372 // Clear the instruction list and skid buffer in case they have any
373 // insts in them.
374 while (!insts[tid].empty()) {
375 insts[tid].pop();
376 }
377
378 while (!skidBuffer[tid].empty()) {
379 skidBuffer[tid].pop();
380 }
381
382 return squash_count;
383}
384
385template<class Impl>
386void
387DefaultDecode<Impl>::skidInsert(ThreadID tid)
388{
389 DynInstPtr inst = NULL;
390
391 while (!insts[tid].empty()) {
392 inst = insts[tid].front();
393
394 insts[tid].pop();
395
396 assert(tid == inst->threadNumber);
397
| 227 }
228
229 return ret_val;
230}
231
232template<class Impl>
233inline bool
234DefaultDecode<Impl>::fetchInstsValid()
235{
236 return fromFetch->size > 0;
237}
238
239template<class Impl>
240bool
241DefaultDecode<Impl>::block(ThreadID tid)
242{
243 DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid);
244
245 // Add the current inputs to the skid buffer so they can be
246 // reprocessed when this stage unblocks.
247 skidInsert(tid);
248
249 // If the decode status is blocked or unblocking then decode has not yet
250 // signalled fetch to unblock. In that case, there is no need to tell
251 // fetch to block.
252 if (decodeStatus[tid] != Blocked) {
253 // Set the status to Blocked.
254 decodeStatus[tid] = Blocked;
255
256 if (toFetch->decodeUnblock[tid]) {
257 toFetch->decodeUnblock[tid] = false;
258 } else {
259 toFetch->decodeBlock[tid] = true;
260 wroteToTimeBuffer = true;
261 }
262
263 return true;
264 }
265
266 return false;
267}
268
269template<class Impl>
270bool
271DefaultDecode<Impl>::unblock(ThreadID tid)
272{
273 // Decode is done unblocking only if the skid buffer is empty.
274 if (skidBuffer[tid].empty()) {
275 DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid);
276 toFetch->decodeUnblock[tid] = true;
277 wroteToTimeBuffer = true;
278
279 decodeStatus[tid] = Running;
280 return true;
281 }
282
283 DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid);
284
285 return false;
286}
287
288template<class Impl>
289void
290DefaultDecode<Impl>::squash(DynInstPtr &inst, ThreadID tid)
291{
292 DPRINTF(Decode, "[tid:%i]: [sn:%i] Squashing due to incorrect branch "
293 "prediction detected at decode.\n", tid, inst->seqNum);
294
295 // Send back mispredict information.
296 toFetch->decodeInfo[tid].branchMispredict = true;
297 toFetch->decodeInfo[tid].predIncorrect = true;
298 toFetch->decodeInfo[tid].mispredictInst = inst;
299 toFetch->decodeInfo[tid].squash = true;
300 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
301 toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
302 toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching();
303 toFetch->decodeInfo[tid].squashInst = inst;
304 if (toFetch->decodeInfo[tid].mispredictInst->isUncondCtrl()) {
305 toFetch->decodeInfo[tid].branchTaken = true;
306 }
307
308 InstSeqNum squash_seq_num = inst->seqNum;
309
310 // Might have to tell fetch to unblock.
311 if (decodeStatus[tid] == Blocked ||
312 decodeStatus[tid] == Unblocking) {
313 toFetch->decodeUnblock[tid] = 1;
314 }
315
316 // Set status to squashing.
317 decodeStatus[tid] = Squashing;
318
319 for (int i=0; i<fromFetch->size; i++) {
320 if (fromFetch->insts[i]->threadNumber == tid &&
321 fromFetch->insts[i]->seqNum > squash_seq_num) {
322 fromFetch->insts[i]->setSquashed();
323 }
324 }
325
326 // Clear the instruction list and skid buffer in case they have any
327 // insts in them.
328 while (!insts[tid].empty()) {
329 insts[tid].pop();
330 }
331
332 while (!skidBuffer[tid].empty()) {
333 skidBuffer[tid].pop();
334 }
335
336 // Squash instructions up until this one
337 cpu->removeInstsUntil(squash_seq_num, tid);
338}
339
340template<class Impl>
341unsigned
342DefaultDecode<Impl>::squash(ThreadID tid)
343{
344 DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid);
345
346 if (decodeStatus[tid] == Blocked ||
347 decodeStatus[tid] == Unblocking) {
348 if (FullSystem) {
349 toFetch->decodeUnblock[tid] = 1;
350 } else {
351 // In syscall emulation, we can have both a block and a squash due
352 // to a syscall in the same cycle. This would cause both signals
353 // to be high. This shouldn't happen in full system.
354 // @todo: Determine if this still happens.
355 if (toFetch->decodeBlock[tid])
356 toFetch->decodeBlock[tid] = 0;
357 else
358 toFetch->decodeUnblock[tid] = 1;
359 }
360 }
361
362 // Set status to squashing.
363 decodeStatus[tid] = Squashing;
364
365 // Go through incoming instructions from fetch and squash them.
366 unsigned squash_count = 0;
367
368 for (int i=0; i<fromFetch->size; i++) {
369 if (fromFetch->insts[i]->threadNumber == tid) {
370 fromFetch->insts[i]->setSquashed();
371 squash_count++;
372 }
373 }
374
375 // Clear the instruction list and skid buffer in case they have any
376 // insts in them.
377 while (!insts[tid].empty()) {
378 insts[tid].pop();
379 }
380
381 while (!skidBuffer[tid].empty()) {
382 skidBuffer[tid].pop();
383 }
384
385 return squash_count;
386}
387
388template<class Impl>
389void
390DefaultDecode<Impl>::skidInsert(ThreadID tid)
391{
392 DynInstPtr inst = NULL;
393
394 while (!insts[tid].empty()) {
395 inst = insts[tid].front();
396
397 insts[tid].pop();
398
399 assert(tid == inst->threadNumber);
400
|
398 DPRINTF(Decode,"Inserting [sn:%lli] PC: %s into decode skidBuffer %i\n",
399 inst->seqNum, inst->pcState(), inst->threadNumber);
400
| |
401 skidBuffer[tid].push(inst);
| 401 skidBuffer[tid].push(inst);
|
| 402
403 DPRINTF(Decode,"Inserting [tid:%d][sn:%lli] PC: %s into decode skidBuffer %i\n",
404 inst->threadNumber, inst->seqNum, inst->pcState(), skidBuffer[tid].size());
|
402 }
403
404 // @todo: Eventually need to enforce this by not letting a thread
405 // fetch past its skidbuffer
406 assert(skidBuffer[tid].size() <= skidBufferMax);
407}
408
409template<class Impl>
410bool
411DefaultDecode<Impl>::skidsEmpty()
412{
413 list<ThreadID>::iterator threads = activeThreads->begin();
414 list<ThreadID>::iterator end = activeThreads->end();
415
416 while (threads != end) {
417 ThreadID tid = *threads++;
418 if (!skidBuffer[tid].empty())
419 return false;
420 }
421
422 return true;
423}
424
425template<class Impl>
426void
427DefaultDecode<Impl>::updateStatus()
428{
429 bool any_unblocking = false;
430
431 list<ThreadID>::iterator threads = activeThreads->begin();
432 list<ThreadID>::iterator end = activeThreads->end();
433
434 while (threads != end) {
435 ThreadID tid = *threads++;
436
437 if (decodeStatus[tid] == Unblocking) {
438 any_unblocking = true;
439 break;
440 }
441 }
442
443 // Decode will have activity if it's unblocking.
444 if (any_unblocking) {
445 if (_status == Inactive) {
446 _status = Active;
447
448 DPRINTF(Activity, "Activating stage.\n");
449
450 cpu->activateStage(O3CPU::DecodeIdx);
451 }
452 } else {
453 // If it's not unblocking, then decode will not have any internal
454 // activity. Switch it to inactive.
455 if (_status == Active) {
456 _status = Inactive;
457 DPRINTF(Activity, "Deactivating stage.\n");
458
459 cpu->deactivateStage(O3CPU::DecodeIdx);
460 }
461 }
462}
463
464template <class Impl>
465void
466DefaultDecode<Impl>::sortInsts()
467{
468 int insts_from_fetch = fromFetch->size;
469 for (int i = 0; i < insts_from_fetch; ++i) {
470 insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]);
471 }
472}
473
474template<class Impl>
475void
476DefaultDecode<Impl>::readStallSignals(ThreadID tid)
477{
478 if (fromRename->renameBlock[tid]) {
479 stalls[tid].rename = true;
480 }
481
482 if (fromRename->renameUnblock[tid]) {
483 assert(stalls[tid].rename);
484 stalls[tid].rename = false;
485 }
| 405 }
406
407 // @todo: Eventually need to enforce this by not letting a thread
408 // fetch past its skidbuffer
409 assert(skidBuffer[tid].size() <= skidBufferMax);
410}
411
412template<class Impl>
413bool
414DefaultDecode<Impl>::skidsEmpty()
415{
416 list<ThreadID>::iterator threads = activeThreads->begin();
417 list<ThreadID>::iterator end = activeThreads->end();
418
419 while (threads != end) {
420 ThreadID tid = *threads++;
421 if (!skidBuffer[tid].empty())
422 return false;
423 }
424
425 return true;
426}
427
428template<class Impl>
429void
430DefaultDecode<Impl>::updateStatus()
431{
432 bool any_unblocking = false;
433
434 list<ThreadID>::iterator threads = activeThreads->begin();
435 list<ThreadID>::iterator end = activeThreads->end();
436
437 while (threads != end) {
438 ThreadID tid = *threads++;
439
440 if (decodeStatus[tid] == Unblocking) {
441 any_unblocking = true;
442 break;
443 }
444 }
445
446 // Decode will have activity if it's unblocking.
447 if (any_unblocking) {
448 if (_status == Inactive) {
449 _status = Active;
450
451 DPRINTF(Activity, "Activating stage.\n");
452
453 cpu->activateStage(O3CPU::DecodeIdx);
454 }
455 } else {
456 // If it's not unblocking, then decode will not have any internal
457 // activity. Switch it to inactive.
458 if (_status == Active) {
459 _status = Inactive;
460 DPRINTF(Activity, "Deactivating stage.\n");
461
462 cpu->deactivateStage(O3CPU::DecodeIdx);
463 }
464 }
465}
466
467template <class Impl>
468void
469DefaultDecode<Impl>::sortInsts()
470{
471 int insts_from_fetch = fromFetch->size;
472 for (int i = 0; i < insts_from_fetch; ++i) {
473 insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]);
474 }
475}
476
477template<class Impl>
478void
479DefaultDecode<Impl>::readStallSignals(ThreadID tid)
480{
481 if (fromRename->renameBlock[tid]) {
482 stalls[tid].rename = true;
483 }
484
485 if (fromRename->renameUnblock[tid]) {
486 assert(stalls[tid].rename);
487 stalls[tid].rename = false;
488 }
|
486
487 if (fromIEW->iewBlock[tid]) {
488 stalls[tid].iew = true;
489 }
490
491 if (fromIEW->iewUnblock[tid]) {
492 assert(stalls[tid].iew);
493 stalls[tid].iew = false;
494 }
495
496 if (fromCommit->commitBlock[tid]) {
497 stalls[tid].commit = true;
498 }
499
500 if (fromCommit->commitUnblock[tid]) {
501 assert(stalls[tid].commit);
502 stalls[tid].commit = false;
503 }
| |
504}
505
506template <class Impl>
507bool
508DefaultDecode<Impl>::checkSignalsAndUpdate(ThreadID tid)
509{
510 // Check if there's a squash signal, squash if there is.
511 // Check stall signals, block if necessary.
512 // If status was blocked
513 // Check if stall conditions have passed
514 // if so then go to unblocking
515 // If status was Squashing
516 // check if squashing is not high. Switch to running this cycle.
517
518 // Update the per thread stall statuses.
519 readStallSignals(tid);
520
521 // Check squash signals from commit.
522 if (fromCommit->commitInfo[tid].squash) {
523
524 DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash "
525 "from commit.\n", tid);
526
527 squash(tid);
528
529 return true;
530 }
531
| 489}
490
491template <class Impl>
492bool
493DefaultDecode<Impl>::checkSignalsAndUpdate(ThreadID tid)
494{
495 // Check if there's a squash signal, squash if there is.
496 // Check stall signals, block if necessary.
497 // If status was blocked
498 // Check if stall conditions have passed
499 // if so then go to unblocking
500 // If status was Squashing
501 // check if squashing is not high. Switch to running this cycle.
502
503 // Update the per thread stall statuses.
504 readStallSignals(tid);
505
506 // Check squash signals from commit.
507 if (fromCommit->commitInfo[tid].squash) {
508
509 DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash "
510 "from commit.\n", tid);
511
512 squash(tid);
513
514 return true;
515 }
516
|
532 // Check ROB squash signals from commit.
533 if (fromCommit->commitInfo[tid].robSquashing) {
534 DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid);
535
536 // Continue to squash.
537 decodeStatus[tid] = Squashing;
538
539 return true;
540 }
541
| |
542 if (checkStall(tid)) {
543 return block(tid);
544 }
545
546 if (decodeStatus[tid] == Blocked) {
547 DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n",
548 tid);
549
550 decodeStatus[tid] = Unblocking;
551
552 unblock(tid);
553
554 return true;
555 }
556
557 if (decodeStatus[tid] == Squashing) {
558 // Switch status to running if decode isn't being told to block or
559 // squash this cycle.
560 DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n",
561 tid);
562
563 decodeStatus[tid] = Running;
564
565 return false;
566 }
567
568 // If we've reached this point, we have not gotten any signals that
569 // cause decode to change its status. Decode remains the same as before.
570 return false;
571}
572
573template<class Impl>
574void
575DefaultDecode<Impl>::tick()
576{
577 wroteToTimeBuffer = false;
578
579 bool status_change = false;
580
581 toRenameIndex = 0;
582
583 list<ThreadID>::iterator threads = activeThreads->begin();
584 list<ThreadID>::iterator end = activeThreads->end();
585
586 sortInsts();
587
588 //Check stall and squash signals.
589 while (threads != end) {
590 ThreadID tid = *threads++;
591
592 DPRINTF(Decode,"Processing [tid:%i]\n",tid);
593 status_change = checkSignalsAndUpdate(tid) || status_change;
594
595 decode(status_change, tid);
596 }
597
598 if (status_change) {
599 updateStatus();
600 }
601
602 if (wroteToTimeBuffer) {
603 DPRINTF(Activity, "Activity this cycle.\n");
604
605 cpu->activityThisCycle();
606 }
607}
608
609template<class Impl>
610void
611DefaultDecode<Impl>::decode(bool &status_change, ThreadID tid)
612{
613 // If status is Running or idle,
614 // call decodeInsts()
615 // If status is Unblocking,
616 // buffer any instructions coming from fetch
617 // continue trying to empty skid buffer
618 // check if stall conditions have passed
619
620 if (decodeStatus[tid] == Blocked) {
621 ++decodeBlockedCycles;
622 } else if (decodeStatus[tid] == Squashing) {
623 ++decodeSquashCycles;
624 }
625
626 // Decode should try to decode as many instructions as its bandwidth
627 // will allow, as long as it is not currently blocked.
628 if (decodeStatus[tid] == Running ||
629 decodeStatus[tid] == Idle) {
630 DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run "
631 "stage.\n",tid);
632
633 decodeInsts(tid);
634 } else if (decodeStatus[tid] == Unblocking) {
635 // Make sure that the skid buffer has something in it if the
636 // status is unblocking.
637 assert(!skidsEmpty());
638
639 // If the status was unblocking, then instructions from the skid
640 // buffer were used. Remove those instructions and handle
641 // the rest of unblocking.
642 decodeInsts(tid);
643
644 if (fetchInstsValid()) {
645 // Add the current inputs to the skid buffer so they can be
646 // reprocessed when this stage unblocks.
647 skidInsert(tid);
648 }
649
650 status_change = unblock(tid) || status_change;
651 }
652}
653
654template <class Impl>
655void
656DefaultDecode<Impl>::decodeInsts(ThreadID tid)
657{
658 // Instructions can come either from the skid buffer or the list of
659 // instructions coming from fetch, depending on decode's status.
660 int insts_available = decodeStatus[tid] == Unblocking ?
661 skidBuffer[tid].size() : insts[tid].size();
662
663 if (insts_available == 0) {
664 DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out"
665 " early.\n",tid);
666 // Should I change the status to idle?
667 ++decodeIdleCycles;
668 return;
669 } else if (decodeStatus[tid] == Unblocking) {
670 DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid "
671 "buffer.\n",tid);
672 ++decodeUnblockCycles;
673 } else if (decodeStatus[tid] == Running) {
674 ++decodeRunCycles;
675 }
676
677 DynInstPtr inst;
678
679 std::queue<DynInstPtr>
680 &insts_to_decode = decodeStatus[tid] == Unblocking ?
681 skidBuffer[tid] : insts[tid];
682
683 DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid);
684
685 while (insts_available > 0 && toRenameIndex < decodeWidth) {
686 assert(!insts_to_decode.empty());
687
688 inst = insts_to_decode.front();
689
690 insts_to_decode.pop();
691
692 DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with "
693 "PC %s\n", tid, inst->seqNum, inst->pcState());
694
695 if (inst->isSquashed()) {
696 DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %s is "
697 "squashed, skipping.\n",
698 tid, inst->seqNum, inst->pcState());
699
700 ++decodeSquashedInsts;
701
702 --insts_available;
703
704 continue;
705 }
706
707 // Also check if instructions have no source registers. Mark
708 // them as ready to issue at any time. Not sure if this check
709 // should exist here or at a later stage; however it doesn't matter
710 // too much for function correctness.
711 if (inst->numSrcRegs() == 0) {
712 inst->setCanIssue();
713 }
714
715 // This current instruction is valid, so add it into the decode
716 // queue. The next instruction may not be valid, so check to
717 // see if branches were predicted correctly.
718 toRename->insts[toRenameIndex] = inst;
719
720 ++(toRename->size);
721 ++toRenameIndex;
722 ++decodeDecodedInsts;
723 --insts_available;
724
725#if TRACING_ON
726 if (DTRACE(O3PipeView)) {
727 inst->decodeTick = curTick() - inst->fetchTick;
728 }
729#endif
730
731 // Ensure that if it was predicted as a branch, it really is a
732 // branch.
733 if (inst->readPredTaken() && !inst->isControl()) {
734 panic("Instruction predicted as a branch!");
735
736 ++decodeControlMispred;
737
738 // Might want to set some sort of boolean and just do
739 // a check at the end
740 squash(inst, inst->threadNumber);
741
742 break;
743 }
744
745 // Go ahead and compute any PC-relative branches.
746 if (inst->isDirectCtrl() && inst->isUncondCtrl()) {
747 ++decodeBranchResolved;
748
749 if (!(inst->branchTarget() == inst->readPredTarg())) {
750 ++decodeBranchMispred;
751
752 // Might want to set some sort of boolean and just do
753 // a check at the end
754 squash(inst, inst->threadNumber);
755 TheISA::PCState target = inst->branchTarget();
756
757 DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %s\n",
758 inst->seqNum, target);
759 //The micro pc after an instruction level branch should be 0
760 inst->setPredTarg(target);
761 break;
762 }
763 }
764 }
765
766 // If we didn't process all instructions, then we will need to block
767 // and put all those instructions into the skid buffer.
768 if (!insts_to_decode.empty()) {
769 block(tid);
770 }
771
772 // Record that decode has written to the time buffer for activity
773 // tracking.
774 if (toRenameIndex) {
775 wroteToTimeBuffer = true;
776 }
777}
778
779#endif//__CPU_O3_DECODE_IMPL_HH__
| 517 if (checkStall(tid)) {
518 return block(tid);
519 }
520
521 if (decodeStatus[tid] == Blocked) {
522 DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n",
523 tid);
524
525 decodeStatus[tid] = Unblocking;
526
527 unblock(tid);
528
529 return true;
530 }
531
532 if (decodeStatus[tid] == Squashing) {
533 // Switch status to running if decode isn't being told to block or
534 // squash this cycle.
535 DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n",
536 tid);
537
538 decodeStatus[tid] = Running;
539
540 return false;
541 }
542
543 // If we've reached this point, we have not gotten any signals that
544 // cause decode to change its status. Decode remains the same as before.
545 return false;
546}
547
548template<class Impl>
549void
550DefaultDecode<Impl>::tick()
551{
552 wroteToTimeBuffer = false;
553
554 bool status_change = false;
555
556 toRenameIndex = 0;
557
558 list<ThreadID>::iterator threads = activeThreads->begin();
559 list<ThreadID>::iterator end = activeThreads->end();
560
561 sortInsts();
562
563 //Check stall and squash signals.
564 while (threads != end) {
565 ThreadID tid = *threads++;
566
567 DPRINTF(Decode,"Processing [tid:%i]\n",tid);
568 status_change = checkSignalsAndUpdate(tid) || status_change;
569
570 decode(status_change, tid);
571 }
572
573 if (status_change) {
574 updateStatus();
575 }
576
577 if (wroteToTimeBuffer) {
578 DPRINTF(Activity, "Activity this cycle.\n");
579
580 cpu->activityThisCycle();
581 }
582}
583
584template<class Impl>
585void
586DefaultDecode<Impl>::decode(bool &status_change, ThreadID tid)
587{
588 // If status is Running or idle,
589 // call decodeInsts()
590 // If status is Unblocking,
591 // buffer any instructions coming from fetch
592 // continue trying to empty skid buffer
593 // check if stall conditions have passed
594
595 if (decodeStatus[tid] == Blocked) {
596 ++decodeBlockedCycles;
597 } else if (decodeStatus[tid] == Squashing) {
598 ++decodeSquashCycles;
599 }
600
601 // Decode should try to decode as many instructions as its bandwidth
602 // will allow, as long as it is not currently blocked.
603 if (decodeStatus[tid] == Running ||
604 decodeStatus[tid] == Idle) {
605 DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run "
606 "stage.\n",tid);
607
608 decodeInsts(tid);
609 } else if (decodeStatus[tid] == Unblocking) {
610 // Make sure that the skid buffer has something in it if the
611 // status is unblocking.
612 assert(!skidsEmpty());
613
614 // If the status was unblocking, then instructions from the skid
615 // buffer were used. Remove those instructions and handle
616 // the rest of unblocking.
617 decodeInsts(tid);
618
619 if (fetchInstsValid()) {
620 // Add the current inputs to the skid buffer so they can be
621 // reprocessed when this stage unblocks.
622 skidInsert(tid);
623 }
624
625 status_change = unblock(tid) || status_change;
626 }
627}
628
629template <class Impl>
630void
631DefaultDecode<Impl>::decodeInsts(ThreadID tid)
632{
633 // Instructions can come either from the skid buffer or the list of
634 // instructions coming from fetch, depending on decode's status.
635 int insts_available = decodeStatus[tid] == Unblocking ?
636 skidBuffer[tid].size() : insts[tid].size();
637
638 if (insts_available == 0) {
639 DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out"
640 " early.\n",tid);
641 // Should I change the status to idle?
642 ++decodeIdleCycles;
643 return;
644 } else if (decodeStatus[tid] == Unblocking) {
645 DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid "
646 "buffer.\n",tid);
647 ++decodeUnblockCycles;
648 } else if (decodeStatus[tid] == Running) {
649 ++decodeRunCycles;
650 }
651
652 DynInstPtr inst;
653
654 std::queue<DynInstPtr>
655 &insts_to_decode = decodeStatus[tid] == Unblocking ?
656 skidBuffer[tid] : insts[tid];
657
658 DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid);
659
660 while (insts_available > 0 && toRenameIndex < decodeWidth) {
661 assert(!insts_to_decode.empty());
662
663 inst = insts_to_decode.front();
664
665 insts_to_decode.pop();
666
667 DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with "
668 "PC %s\n", tid, inst->seqNum, inst->pcState());
669
670 if (inst->isSquashed()) {
671 DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %s is "
672 "squashed, skipping.\n",
673 tid, inst->seqNum, inst->pcState());
674
675 ++decodeSquashedInsts;
676
677 --insts_available;
678
679 continue;
680 }
681
682 // Also check if instructions have no source registers. Mark
683 // them as ready to issue at any time. Not sure if this check
684 // should exist here or at a later stage; however it doesn't matter
685 // too much for function correctness.
686 if (inst->numSrcRegs() == 0) {
687 inst->setCanIssue();
688 }
689
690 // This current instruction is valid, so add it into the decode
691 // queue. The next instruction may not be valid, so check to
692 // see if branches were predicted correctly.
693 toRename->insts[toRenameIndex] = inst;
694
695 ++(toRename->size);
696 ++toRenameIndex;
697 ++decodeDecodedInsts;
698 --insts_available;
699
700#if TRACING_ON
701 if (DTRACE(O3PipeView)) {
702 inst->decodeTick = curTick() - inst->fetchTick;
703 }
704#endif
705
706 // Ensure that if it was predicted as a branch, it really is a
707 // branch.
708 if (inst->readPredTaken() && !inst->isControl()) {
709 panic("Instruction predicted as a branch!");
710
711 ++decodeControlMispred;
712
713 // Might want to set some sort of boolean and just do
714 // a check at the end
715 squash(inst, inst->threadNumber);
716
717 break;
718 }
719
720 // Go ahead and compute any PC-relative branches.
721 if (inst->isDirectCtrl() && inst->isUncondCtrl()) {
722 ++decodeBranchResolved;
723
724 if (!(inst->branchTarget() == inst->readPredTarg())) {
725 ++decodeBranchMispred;
726
727 // Might want to set some sort of boolean and just do
728 // a check at the end
729 squash(inst, inst->threadNumber);
730 TheISA::PCState target = inst->branchTarget();
731
732 DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %s\n",
733 inst->seqNum, target);
734 //The micro pc after an instruction level branch should be 0
735 inst->setPredTarg(target);
736 break;
737 }
738 }
739 }
740
741 // If we didn't process all instructions, then we will need to block
742 // and put all those instructions into the skid buffer.
743 if (!insts_to_decode.empty()) {
744 block(tid);
745 }
746
747 // Record that decode has written to the time buffer for activity
748 // tracking.
749 if (toRenameIndex) {
750 wroteToTimeBuffer = true;
751 }
752}
753
754#endif//__CPU_O3_DECODE_IMPL_HH__
|