1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include "config/the_isa.hh"
32#include "cpu/o3/decode.hh"
33#include "params/DerivO3CPU.hh"
34
35using namespace std;
36
37template<class Impl>
38DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params)
39 : cpu(_cpu),
40 renameToDecodeDelay(params->renameToDecodeDelay),
41 iewToDecodeDelay(params->iewToDecodeDelay),
42 commitToDecodeDelay(params->commitToDecodeDelay),
43 fetchToDecodeDelay(params->fetchToDecodeDelay),
44 decodeWidth(params->decodeWidth),
45 numThreads(params->numThreads)
46{
47 _status = Inactive;
48
49 // Setup status, make sure stall signals are clear.
50 for (ThreadID tid = 0; tid < numThreads; ++tid) {
51 decodeStatus[tid] = Idle;
52
53 stalls[tid].rename = false;
54 stalls[tid].iew = false;
55 stalls[tid].commit = false;
56 }
57
58 // @todo: Make into a parameter
59 skidBufferMax = (fetchToDecodeDelay * params->fetchWidth) + decodeWidth;
60}
61
62template <class Impl>
63std::string
64DefaultDecode<Impl>::name() const
65{
66 return cpu->name() + ".decode";
67}
68
69template <class Impl>
70void
71DefaultDecode<Impl>::regStats()
72{
73 decodeIdleCycles
74 .name(name() + ".DECODE:IdleCycles")
75 .desc("Number of cycles decode is idle")
76 .prereq(decodeIdleCycles);
77 decodeBlockedCycles
78 .name(name() + ".DECODE:BlockedCycles")
79 .desc("Number of cycles decode is blocked")
80 .prereq(decodeBlockedCycles);
81 decodeRunCycles
82 .name(name() + ".DECODE:RunCycles")
83 .desc("Number of cycles decode is running")
84 .prereq(decodeRunCycles);
85 decodeUnblockCycles
86 .name(name() + ".DECODE:UnblockCycles")
87 .desc("Number of cycles decode is unblocking")
88 .prereq(decodeUnblockCycles);
89 decodeSquashCycles
90 .name(name() + ".DECODE:SquashCycles")
91 .desc("Number of cycles decode is squashing")
92 .prereq(decodeSquashCycles);
93 decodeBranchResolved
94 .name(name() + ".DECODE:BranchResolved")
95 .desc("Number of times decode resolved a branch")
96 .prereq(decodeBranchResolved);
97 decodeBranchMispred
98 .name(name() + ".DECODE:BranchMispred")
99 .desc("Number of times decode detected a branch misprediction")
100 .prereq(decodeBranchMispred);
101 decodeControlMispred
102 .name(name() + ".DECODE:ControlMispred")
103 .desc("Number of times decode detected an instruction incorrectly"
104 " predicted as a control")
105 .prereq(decodeControlMispred);
106 decodeDecodedInsts
107 .name(name() + ".DECODE:DecodedInsts")
108 .desc("Number of instructions handled by decode")
109 .prereq(decodeDecodedInsts);
110 decodeSquashedInsts
111 .name(name() + ".DECODE:SquashedInsts")
112 .desc("Number of squashed instructions handled by decode")
113 .prereq(decodeSquashedInsts);
114}
115
116template<class Impl>
117void
118DefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
119{
120 timeBuffer = tb_ptr;
121
122 // Setup wire to write information back to fetch.
123 toFetch = timeBuffer->getWire(0);
124
125 // Create wires to get information from proper places in time buffer.
126 fromRename = timeBuffer->getWire(-renameToDecodeDelay);
127 fromIEW = timeBuffer->getWire(-iewToDecodeDelay);
128 fromCommit = timeBuffer->getWire(-commitToDecodeDelay);
129}
130
131template<class Impl>
132void
133DefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
134{
135 decodeQueue = dq_ptr;
136
137 // Setup wire to write information to proper place in decode queue.
138 toRename = decodeQueue->getWire(0);
139}
140
141template<class Impl>
142void
143DefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
144{
145 fetchQueue = fq_ptr;
146
147 // Setup wire to read information from fetch queue.
148 fromFetch = fetchQueue->getWire(-fetchToDecodeDelay);
149}
150
151template<class Impl>
152void
153DefaultDecode<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr)
154{
155 activeThreads = at_ptr;
156}
157
158template <class Impl>
159bool
160DefaultDecode<Impl>::drain()
161{
162 // Decode is done draining at any time.
163 cpu->signalDrained();
164 return true;
165}
166
167template <class Impl>
168void
169DefaultDecode<Impl>::takeOverFrom()
170{
171 _status = Inactive;
172
173 // Be sure to reset state and clear out any old instructions.
174 for (ThreadID tid = 0; tid < numThreads; ++tid) {
175 decodeStatus[tid] = Idle;
176
177 stalls[tid].rename = false;
178 stalls[tid].iew = false;
179 stalls[tid].commit = false;
180 while (!insts[tid].empty())
181 insts[tid].pop();
182 while (!skidBuffer[tid].empty())
183 skidBuffer[tid].pop();
184 branchCount[tid] = 0;
185 }
186 wroteToTimeBuffer = false;
187}
188
189template<class Impl>
190bool
191DefaultDecode<Impl>::checkStall(ThreadID tid) const
192{
193 bool ret_val = false;
194
195 if (stalls[tid].rename) {
196 DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid);
197 ret_val = true;
198 } else if (stalls[tid].iew) {
199 DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid);
200 ret_val = true;
201 } else if (stalls[tid].commit) {
202 DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid);
203 ret_val = true;
204 }
205
206 return ret_val;
207}
208
209template<class Impl>
210inline bool
211DefaultDecode<Impl>::fetchInstsValid()
212{
213 return fromFetch->size > 0;
214}
215
216template<class Impl>
217bool
218DefaultDecode<Impl>::block(ThreadID tid)
219{
220 DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid);
221
222 // Add the current inputs to the skid buffer so they can be
223 // reprocessed when this stage unblocks.
224 skidInsert(tid);
225
226 // If the decode status is blocked or unblocking then decode has not yet
227 // signalled fetch to unblock. In that case, there is no need to tell
228 // fetch to block.
229 if (decodeStatus[tid] != Blocked) {
230 // Set the status to Blocked.
231 decodeStatus[tid] = Blocked;
232
233 if (decodeStatus[tid] != Unblocking) {
234 toFetch->decodeBlock[tid] = true;
235 wroteToTimeBuffer = true;
236 }
237
238 return true;
239 }
240
241 return false;
242}
243
244template<class Impl>
245bool
246DefaultDecode<Impl>::unblock(ThreadID tid)
247{
248 // Decode is done unblocking only if the skid buffer is empty.
249 if (skidBuffer[tid].empty()) {
250 DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid);
251 toFetch->decodeUnblock[tid] = true;
252 wroteToTimeBuffer = true;
253
254 decodeStatus[tid] = Running;
255 return true;
256 }
257
258 DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid);
259
260 return false;
261}
262
263template<class Impl>
264void
265DefaultDecode<Impl>::squash(DynInstPtr &inst, ThreadID tid)
266{
267 DPRINTF(Decode, "[tid:%i]: [sn:%i] Squashing due to incorrect branch "
268 "prediction detected at decode.\n", tid, inst->seqNum);
269
270 // Send back mispredict information.
271 toFetch->decodeInfo[tid].branchMispredict = true;
272 toFetch->decodeInfo[tid].predIncorrect = true;
273 toFetch->decodeInfo[tid].squash = true;
274 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
275 toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
276 toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching();
277
278 InstSeqNum squash_seq_num = inst->seqNum;
279
280 // Might have to tell fetch to unblock.
281 if (decodeStatus[tid] == Blocked ||
282 decodeStatus[tid] == Unblocking) {
283 toFetch->decodeUnblock[tid] = 1;
284 }
285
286 // Set status to squashing.
287 decodeStatus[tid] = Squashing;
288
289 for (int i=0; i<fromFetch->size; i++) {
290 if (fromFetch->insts[i]->threadNumber == tid &&
291 fromFetch->insts[i]->seqNum > squash_seq_num) {
292 fromFetch->insts[i]->setSquashed();
293 }
294 }
295
296 // Clear the instruction list and skid buffer in case they have any
297 // insts in them.
298 while (!insts[tid].empty()) {
299 insts[tid].pop();
300 }
301
302 while (!skidBuffer[tid].empty()) {
303 skidBuffer[tid].pop();
304 }
305
306 // Squash instructions up until this one
307 cpu->removeInstsUntil(squash_seq_num, tid);
308}
309
310template<class Impl>
311unsigned
312DefaultDecode<Impl>::squash(ThreadID tid)
313{
314 DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid);
315
316 if (decodeStatus[tid] == Blocked ||
317 decodeStatus[tid] == Unblocking) {
318#if !FULL_SYSTEM
319 // In syscall emulation, we can have both a block and a squash due
320 // to a syscall in the same cycle. This would cause both signals to
321 // be high. This shouldn't happen in full system.
322 // @todo: Determine if this still happens.
323 if (toFetch->decodeBlock[tid]) {
324 toFetch->decodeBlock[tid] = 0;
325 } else {
326 toFetch->decodeUnblock[tid] = 1;
327 }
328#else
329 toFetch->decodeUnblock[tid] = 1;
330#endif
331 }
332
333 // Set status to squashing.
334 decodeStatus[tid] = Squashing;
335
336 // Go through incoming instructions from fetch and squash them.
337 unsigned squash_count = 0;
338
339 for (int i=0; i<fromFetch->size; i++) {
340 if (fromFetch->insts[i]->threadNumber == tid) {
341 fromFetch->insts[i]->setSquashed();
342 squash_count++;
343 }
344 }
345
346 // Clear the instruction list and skid buffer in case they have any
347 // insts in them.
348 while (!insts[tid].empty()) {
349 insts[tid].pop();
350 }
351
352 while (!skidBuffer[tid].empty()) {
353 skidBuffer[tid].pop();
354 }
355
356 return squash_count;
357}
358
359template<class Impl>
360void
361DefaultDecode<Impl>::skidInsert(ThreadID tid)
362{
363 DynInstPtr inst = NULL;
364
365 while (!insts[tid].empty()) {
366 inst = insts[tid].front();
367
368 insts[tid].pop();
369
370 assert(tid == inst->threadNumber);
371
372 DPRINTF(Decode,"Inserting [sn:%lli] PC: %s into decode skidBuffer %i\n",
373 inst->seqNum, inst->pcState(), inst->threadNumber);
374
375 skidBuffer[tid].push(inst);
376 }
377
378 // @todo: Eventually need to enforce this by not letting a thread
379 // fetch past its skidbuffer
380 assert(skidBuffer[tid].size() <= skidBufferMax);
381}
382
383template<class Impl>
384bool
385DefaultDecode<Impl>::skidsEmpty()
386{
387 list<ThreadID>::iterator threads = activeThreads->begin();
388 list<ThreadID>::iterator end = activeThreads->end();
389
390 while (threads != end) {
391 ThreadID tid = *threads++;
392 if (!skidBuffer[tid].empty())
393 return false;
394 }
395
396 return true;
397}
398
399template<class Impl>
400void
401DefaultDecode<Impl>::updateStatus()
402{
403 bool any_unblocking = false;
404
405 list<ThreadID>::iterator threads = activeThreads->begin();
406 list<ThreadID>::iterator end = activeThreads->end();
407
408 while (threads != end) {
409 ThreadID tid = *threads++;
410
411 if (decodeStatus[tid] == Unblocking) {
412 any_unblocking = true;
413 break;
414 }
415 }
416
417 // Decode will have activity if it's unblocking.
418 if (any_unblocking) {
419 if (_status == Inactive) {
420 _status = Active;
421
422 DPRINTF(Activity, "Activating stage.\n");
423
424 cpu->activateStage(O3CPU::DecodeIdx);
425 }
426 } else {
427 // If it's not unblocking, then decode will not have any internal
428 // activity. Switch it to inactive.
429 if (_status == Active) {
430 _status = Inactive;
431 DPRINTF(Activity, "Deactivating stage.\n");
432
433 cpu->deactivateStage(O3CPU::DecodeIdx);
434 }
435 }
436}
437
438template <class Impl>
439void
440DefaultDecode<Impl>::sortInsts()
441{
442 int insts_from_fetch = fromFetch->size;
443#ifdef DEBUG
444 for (ThreadID tid = 0; tid < numThreads; tid++)
445 assert(insts[tid].empty());
446#endif
447 for (int i = 0; i < insts_from_fetch; ++i) {
448 insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]);
449 }
450}
451
452template<class Impl>
453void
454DefaultDecode<Impl>::readStallSignals(ThreadID tid)
455{
456 if (fromRename->renameBlock[tid]) {
457 stalls[tid].rename = true;
458 }
459
460 if (fromRename->renameUnblock[tid]) {
461 assert(stalls[tid].rename);
462 stalls[tid].rename = false;
463 }
464
465 if (fromIEW->iewBlock[tid]) {
466 stalls[tid].iew = true;
467 }
468
469 if (fromIEW->iewUnblock[tid]) {
470 assert(stalls[tid].iew);
471 stalls[tid].iew = false;
472 }
473
474 if (fromCommit->commitBlock[tid]) {
475 stalls[tid].commit = true;
476 }
477
478 if (fromCommit->commitUnblock[tid]) {
479 assert(stalls[tid].commit);
480 stalls[tid].commit = false;
481 }
482}
483
484template <class Impl>
485bool
486DefaultDecode<Impl>::checkSignalsAndUpdate(ThreadID tid)
487{
488 // Check if there's a squash signal, squash if there is.
489 // Check stall signals, block if necessary.
490 // If status was blocked
491 // Check if stall conditions have passed
492 // if so then go to unblocking
493 // If status was Squashing
494 // check if squashing is not high. Switch to running this cycle.
495
496 // Update the per thread stall statuses.
497 readStallSignals(tid);
498
499 // Check squash signals from commit.
500 if (fromCommit->commitInfo[tid].squash) {
501
502 DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash "
503 "from commit.\n", tid);
504
505 squash(tid);
506
507 return true;
508 }
509
510 // Check ROB squash signals from commit.
511 if (fromCommit->commitInfo[tid].robSquashing) {
512 DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid);
513
514 // Continue to squash.
515 decodeStatus[tid] = Squashing;
516
517 return true;
518 }
519
520 if (checkStall(tid)) {
521 return block(tid);
522 }
523
524 if (decodeStatus[tid] == Blocked) {
525 DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n",
526 tid);
527
528 decodeStatus[tid] = Unblocking;
529
530 unblock(tid);
531
532 return true;
533 }
534
535 if (decodeStatus[tid] == Squashing) {
536 // Switch status to running if decode isn't being told to block or
537 // squash this cycle.
538 DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n",
539 tid);
540
541 decodeStatus[tid] = Running;
542
543 return false;
544 }
545
546 // If we've reached this point, we have not gotten any signals that
547 // cause decode to change its status. Decode remains the same as before.
548 return false;
549}
550
551template<class Impl>
552void
553DefaultDecode<Impl>::tick()
554{
555 wroteToTimeBuffer = false;
556
557 bool status_change = false;
558
559 toRenameIndex = 0;
560
561 list<ThreadID>::iterator threads = activeThreads->begin();
562 list<ThreadID>::iterator end = activeThreads->end();
563
564 sortInsts();
565
566 //Check stall and squash signals.
567 while (threads != end) {
568 ThreadID tid = *threads++;
569
570 DPRINTF(Decode,"Processing [tid:%i]\n",tid);
571 status_change = checkSignalsAndUpdate(tid) || status_change;
572
573 decode(status_change, tid);
574 }
575
576 if (status_change) {
577 updateStatus();
578 }
579
580 if (wroteToTimeBuffer) {
581 DPRINTF(Activity, "Activity this cycle.\n");
582
583 cpu->activityThisCycle();
584 }
585}
586
587template<class Impl>
588void
589DefaultDecode<Impl>::decode(bool &status_change, ThreadID tid)
590{
591 // If status is Running or idle,
592 // call decodeInsts()
593 // If status is Unblocking,
594 // buffer any instructions coming from fetch
595 // continue trying to empty skid buffer
596 // check if stall conditions have passed
597
598 if (decodeStatus[tid] == Blocked) {
599 ++decodeBlockedCycles;
600 } else if (decodeStatus[tid] == Squashing) {
601 ++decodeSquashCycles;
602 }
603
604 // Decode should try to decode as many instructions as its bandwidth
605 // will allow, as long as it is not currently blocked.
606 if (decodeStatus[tid] == Running ||
607 decodeStatus[tid] == Idle) {
608 DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run "
609 "stage.\n",tid);
610
611 decodeInsts(tid);
612 } else if (decodeStatus[tid] == Unblocking) {
613 // Make sure that the skid buffer has something in it if the
614 // status is unblocking.
615 assert(!skidsEmpty());
616
617 // If the status was unblocking, then instructions from the skid
618 // buffer were used. Remove those instructions and handle
619 // the rest of unblocking.
620 decodeInsts(tid);
621
622 if (fetchInstsValid()) {
623 // Add the current inputs to the skid buffer so they can be
624 // reprocessed when this stage unblocks.
625 skidInsert(tid);
626 }
627
628 status_change = unblock(tid) || status_change;
629 }
630}
631
632template <class Impl>
633void
634DefaultDecode<Impl>::decodeInsts(ThreadID tid)
635{
636 // Instructions can come either from the skid buffer or the list of
637 // instructions coming from fetch, depending on decode's status.
638 int insts_available = decodeStatus[tid] == Unblocking ?
639 skidBuffer[tid].size() : insts[tid].size();
640
641 if (insts_available == 0) {
642 DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out"
643 " early.\n",tid);
644 // Should I change the status to idle?
645 ++decodeIdleCycles;
646 return;
647 } else if (decodeStatus[tid] == Unblocking) {
648 DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid "
649 "buffer.\n",tid);
650 ++decodeUnblockCycles;
651 } else if (decodeStatus[tid] == Running) {
652 ++decodeRunCycles;
653 }
654
655 DynInstPtr inst;
656
657 std::queue<DynInstPtr>
658 &insts_to_decode = decodeStatus[tid] == Unblocking ?
659 skidBuffer[tid] : insts[tid];
660
661 DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid);
662
663 while (insts_available > 0 && toRenameIndex < decodeWidth) {
664 assert(!insts_to_decode.empty());
665
666 inst = insts_to_decode.front();
667
668 insts_to_decode.pop();
669
670 DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with "
671 "PC %s\n", tid, inst->seqNum, inst->pcState());
672
673 if (inst->isSquashed()) {
674 DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %s is "
675 "squashed, skipping.\n",
676 tid, inst->seqNum, inst->pcState());
677
678 ++decodeSquashedInsts;
679
680 --insts_available;
681
682 continue;
683 }
684
685 // Also check if instructions have no source registers. Mark
686 // them as ready to issue at any time. Not sure if this check
687 // should exist here or at a later stage; however it doesn't matter
688 // too much for function correctness.
689 if (inst->numSrcRegs() == 0) {
690 inst->setCanIssue();
691 }
692
693 // This current instruction is valid, so add it into the decode
694 // queue. The next instruction may not be valid, so check to
695 // see if branches were predicted correctly.
696 toRename->insts[toRenameIndex] = inst;
697
698 ++(toRename->size);
699 ++toRenameIndex;
700 ++decodeDecodedInsts;
701 --insts_available;
702
703 // Ensure that if it was predicted as a branch, it really is a
704 // branch.
705 if (inst->readPredTaken() && !inst->isControl()) {
706 panic("Instruction predicted as a branch!");
707
708 ++decodeControlMispred;
709
710 // Might want to set some sort of boolean and just do
711 // a check at the end
712 squash(inst, inst->threadNumber);
713
714 break;
715 }
716
717 // Go ahead and compute any PC-relative branches.
718 if (inst->isDirectCtrl() && inst->isUncondCtrl()) {
719 ++decodeBranchResolved;
720
721 if (!(inst->branchTarget() == inst->readPredTarg())) {
722 ++decodeBranchMispred;
723
724 // Might want to set some sort of boolean and just do
725 // a check at the end
726 squash(inst, inst->threadNumber);
727 TheISA::PCState target = inst->branchTarget();
728
729 DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %s\n",
730 inst->seqNum, target);
731 //The micro pc after an instruction level branch should be 0
732 inst->setPredTarg(target);
733 break;
734 }
735 }
736 }
737
738 // If we didn't process all instructions, then we will need to block
739 // and put all those instructions into the skid buffer.
740 if (!insts_to_decode.empty()) {
741 block(tid);
742 }
743
744 // Record that decode has written to the time buffer for activity
745 // tracking.
746 if (toRenameIndex) {
747 wroteToTimeBuffer = true;
748 }
749}