1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 410 unchanged lines hidden (view full) ---

419 // fetch past its skidbuffer
420 assert(skidBuffer[tid].size() <= skidBufferMax);
421}
422
423template<class Impl>
424bool
425DefaultDecode<Impl>::skidsEmpty()
426{
427 std::list<unsigned>::iterator threads = (*activeThreads).begin();
428
429 while (threads != (*activeThreads).end()) {
430 if (!skidBuffer[*threads++].empty())
431 return false;
432 }
433
434 return true;
435}
436
437template<class Impl>
438void
439DefaultDecode<Impl>::updateStatus()
440{
441 bool any_unblocking = false;
442
443 std::list<unsigned>::iterator threads = (*activeThreads).begin();
444
445 threads = (*activeThreads).begin();
446
447 while (threads != (*activeThreads).end()) {
448 unsigned tid = *threads++;
449
450 if (decodeStatus[tid] == Unblocking) {
451 any_unblocking = true;
452 break;
453 }
454 }
455

--- 136 unchanged lines hidden (view full) ---

592DefaultDecode<Impl>::tick()
593{
594 wroteToTimeBuffer = false;
595
596 bool status_change = false;
597
598 toRenameIndex = 0;
599
600 std::list<unsigned>::iterator threads = (*activeThreads).begin();
601
602 sortInsts();
603
604 //Check stall and squash signals.
605 while (threads != (*activeThreads).end()) {
606 unsigned tid = *threads++;
607
608 DPRINTF(Decode,"Processing [tid:%i]\n",tid);
609 status_change = checkSignalsAndUpdate(tid) || status_change;
610
611 decode(status_change, tid);
612 }
613
614 if (status_change) {

--- 121 unchanged lines hidden (view full) ---

736
737 ++(toRename->size);
738 ++toRenameIndex;
739 ++decodeDecodedInsts;
740 --insts_available;
741
742 // Ensure that if it was predicted as a branch, it really is a
743 // branch.
744 if (inst->readPredTaken() && !inst->isControl()) {
745 DPRINTF(Decode, "PredPC : %#x != NextPC: %#x\n",inst->predPC,
746 inst->nextPC + 4);
747
748 panic("Instruction predicted as a branch!");
749
750 ++decodeControlMispred;
751
752 // Might want to set some sort of boolean and just do
753 // a check at the end
754 squash(inst, inst->threadNumber);
755
756 break;
757 }
758
759 // Go ahead and compute any PC-relative branches.
760 if (inst->isDirectCtrl() && inst->isUncondCtrl()) {
761 ++decodeBranchResolved;
762
763 if (inst->branchTarget() != inst->readPredPC()) {
764 ++decodeBranchMispred;
765
766 // Might want to set some sort of boolean and just do
767 // a check at the end
768#if !ISA_HAS_DELAY_SLOT
769 squash(inst, inst->threadNumber);
770 Addr target = inst->branchTarget();
771 inst->setPredTarg(target, target + sizeof(TheISA::MachInst));
772 break;
773#else
774 // If mispredicted as taken, then ignore delay slot
775 // instruction... else keep delay slot and squash
776 // after it is sent to rename
777 if (inst->readPredTaken() && inst->isCondDelaySlot()) {
778 DPRINTF(Decode, "[tid:%i]: Conditional delay slot inst."
779 "[sn:%i] PC %#x mispredicted as taken.\n", tid,
780 inst->seqNum, inst->PC);
781 bdelayDoneSeqNum[tid] = inst->seqNum;
782 squash(inst, inst->threadNumber);
783 Addr target = inst->branchTarget();
784 inst->setPredTarg(target,
785 target + sizeof(TheISA::MachInst));
786 break;
787 } else {
788 DPRINTF(Decode, "[tid:%i]: Misprediction detected at "
789 "[sn:%i] PC %#x, will squash after delay slot "
790 "inst. is sent to Rename\n",
791 tid, inst->seqNum, inst->PC);
792 bdelayDoneSeqNum[tid] = inst->seqNum + 1;
793 squashAfterDelaySlot[tid] = true;
794 squashInst[tid] = inst;
795 continue;
796 }
797#endif
798 }
799 }
800
801 if (squashAfterDelaySlot[tid]) {
802 assert(!inst->isSquashed());
803 squash(squashInst[tid], squashInst[tid]->threadNumber);
804 Addr target = squashInst[tid]->branchTarget();
805 squashInst[tid]->setPredTarg(target,
806 target + sizeof(TheISA::MachInst));
807 assert(!inst->isSquashed());
808 break;
809 }
810 }
811
812 // If we didn't process all instructions, then we will need to block
813 // and put all those instructions into the skid buffer.
814 if (!insts_to_decode.empty()) {
815 block(tid);
816 }
817
818 // Record that decode has written to the time buffer for activity
819 // tracking.
820 if (toRenameIndex) {
821 wroteToTimeBuffer = true;
822 }
823}