1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

--- 79 unchanged lines hidden (view full) ---

90{
91 _status = Inactive;
92
93 // Setup status, make sure stall signals are clear.
94 for (ThreadID tid = 0; tid < numThreads; ++tid) {
95 decodeStatus[tid] = Idle;
96
97 stalls[tid].rename = false;
98 stalls[tid].iew = false;
99 stalls[tid].commit = false;
100 }
101}
102
103template <class Impl>
104std::string
105DefaultDecode<Impl>::name() const
106{
107 return cpu->name() + ".decode";

--- 93 unchanged lines hidden (view full) ---

201DefaultDecode<Impl>::drainSanityCheck() const
202{
203 for (ThreadID tid = 0; tid < numThreads; ++tid) {
204 assert(insts[tid].empty());
205 assert(skidBuffer[tid].empty());
206 }
207}
208
209template<class Impl>
210bool
211DefaultDecode<Impl>::checkStall(ThreadID tid) const
212{
213 bool ret_val = false;
214
215 if (stalls[tid].rename) {
216 DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid);
217 ret_val = true;
218 } else if (stalls[tid].iew) {
219 DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid);
220 ret_val = true;
221 } else if (stalls[tid].commit) {
222 DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid);
223 ret_val = true;
224 }
225
226 return ret_val;
227}
228
229template<class Impl>
230inline bool
231DefaultDecode<Impl>::fetchInstsValid()

--- 158 unchanged lines hidden (view full) ---

390
391 while (!insts[tid].empty()) {
392 inst = insts[tid].front();
393
394 insts[tid].pop();
395
396 assert(tid == inst->threadNumber);
397
398 DPRINTF(Decode,"Inserting [sn:%lli] PC: %s into decode skidBuffer %i\n",
399 inst->seqNum, inst->pcState(), inst->threadNumber);
400
401 skidBuffer[tid].push(inst);
402 }
403
404 // @todo: Eventually need to enforce this by not letting a thread
405 // fetch past its skidbuffer
406 assert(skidBuffer[tid].size() <= skidBufferMax);
407}
408
409template<class Impl>

--- 68 unchanged lines hidden (view full) ---

478 if (fromRename->renameBlock[tid]) {
479 stalls[tid].rename = true;
480 }
481
482 if (fromRename->renameUnblock[tid]) {
483 assert(stalls[tid].rename);
484 stalls[tid].rename = false;
485 }
486
487 if (fromIEW->iewBlock[tid]) {
488 stalls[tid].iew = true;
489 }
490
491 if (fromIEW->iewUnblock[tid]) {
492 assert(stalls[tid].iew);
493 stalls[tid].iew = false;
494 }
495
496 if (fromCommit->commitBlock[tid]) {
497 stalls[tid].commit = true;
498 }
499
500 if (fromCommit->commitUnblock[tid]) {
501 assert(stalls[tid].commit);
502 stalls[tid].commit = false;
503 }
504}
505
506template <class Impl>
507bool
508DefaultDecode<Impl>::checkSignalsAndUpdate(ThreadID tid)
509{
510 // Check if there's a squash signal, squash if there is.
511 // Check stall signals, block if necessary.

--- 12 unchanged lines hidden (view full) ---

524 DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash "
525 "from commit.\n", tid);
526
527 squash(tid);
528
529 return true;
530 }
531
532 // Check ROB squash signals from commit.
533 if (fromCommit->commitInfo[tid].robSquashing) {
534 DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid);
535
536 // Continue to squash.
537 decodeStatus[tid] = Squashing;
538
539 return true;
540 }
541
542 if (checkStall(tid)) {
543 return block(tid);
544 }
545
546 if (decodeStatus[tid] == Blocked) {
547 DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n",
548 tid);
549

--- 230 unchanged lines hidden ---