1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_O3_DECODE_IMPL_HH__
44#define __CPU_O3_DECODE_IMPL_HH__
45
46#include "arch/types.hh"
47#include "base/trace.hh"
48#include "config/the_isa.hh"
49#include "cpu/o3/decode.hh"
50#include "cpu/inst_seq.hh"
51#include "debug/Activity.hh"
52#include "debug/Decode.hh"
53#include "debug/O3PipeView.hh"
54#include "params/DerivO3CPU.hh"
55#include "sim/full_system.hh"
56
57// clang complains about std::set being overloaded with Packet::set if
58// we open up the entire namespace std
59using std::list;
60
61template<class Impl>
62DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params)
63 : cpu(_cpu),
64 renameToDecodeDelay(params->renameToDecodeDelay),
65 iewToDecodeDelay(params->iewToDecodeDelay),
66 commitToDecodeDelay(params->commitToDecodeDelay),
67 fetchToDecodeDelay(params->fetchToDecodeDelay),
68 decodeWidth(params->decodeWidth),
69 numThreads(params->numThreads)
70{
71 // @todo: Make into a parameter
72 skidBufferMax = (fetchToDecodeDelay + 1) * params->fetchWidth;
73}
74
75template<class Impl>
76void
77DefaultDecode<Impl>::startupStage()
78{
79 resetStage();
80}
81
82template<class Impl>
83void
84DefaultDecode<Impl>::resetStage()
85{
86 _status = Inactive;
87
88 // Setup status, make sure stall signals are clear.
89 for (ThreadID tid = 0; tid < numThreads; ++tid) {
90 decodeStatus[tid] = Idle;
91
92 stalls[tid].rename = false;
93 stalls[tid].iew = false;
94 stalls[tid].commit = false;
95 }
96}
97
98template <class Impl>
99std::string
100DefaultDecode<Impl>::name() const
101{
102 return cpu->name() + ".decode";
103}
104
105template <class Impl>
106void
107DefaultDecode<Impl>::regStats()
108{
109 decodeIdleCycles
110 .name(name() + ".IdleCycles")
111 .desc("Number of cycles decode is idle")
112 .prereq(decodeIdleCycles);
113 decodeBlockedCycles
114 .name(name() + ".BlockedCycles")
115 .desc("Number of cycles decode is blocked")
116 .prereq(decodeBlockedCycles);
117 decodeRunCycles
118 .name(name() + ".RunCycles")
119 .desc("Number of cycles decode is running")
120 .prereq(decodeRunCycles);
121 decodeUnblockCycles
122 .name(name() + ".UnblockCycles")
123 .desc("Number of cycles decode is unblocking")
124 .prereq(decodeUnblockCycles);
125 decodeSquashCycles
126 .name(name() + ".SquashCycles")
127 .desc("Number of cycles decode is squashing")
128 .prereq(decodeSquashCycles);
129 decodeBranchResolved
130 .name(name() + ".BranchResolved")
131 .desc("Number of times decode resolved a branch")
132 .prereq(decodeBranchResolved);
133 decodeBranchMispred
134 .name(name() + ".BranchMispred")
135 .desc("Number of times decode detected a branch misprediction")
136 .prereq(decodeBranchMispred);
137 decodeControlMispred
138 .name(name() + ".ControlMispred")
139 .desc("Number of times decode detected an instruction incorrectly"
140 " predicted as a control")
141 .prereq(decodeControlMispred);
142 decodeDecodedInsts
143 .name(name() + ".DecodedInsts")
144 .desc("Number of instructions handled by decode")
145 .prereq(decodeDecodedInsts);
146 decodeSquashedInsts
147 .name(name() + ".SquashedInsts")
148 .desc("Number of squashed instructions handled by decode")
149 .prereq(decodeSquashedInsts);
150}
151
152template<class Impl>
153void
154DefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
155{
156 timeBuffer = tb_ptr;
157
158 // Setup wire to write information back to fetch.
159 toFetch = timeBuffer->getWire(0);
160
161 // Create wires to get information from proper places in time buffer.
162 fromRename = timeBuffer->getWire(-renameToDecodeDelay);
163 fromIEW = timeBuffer->getWire(-iewToDecodeDelay);
164 fromCommit = timeBuffer->getWire(-commitToDecodeDelay);
165}
166
167template<class Impl>
168void
169DefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
170{
171 decodeQueue = dq_ptr;
172
173 // Setup wire to write information to proper place in decode queue.
174 toRename = decodeQueue->getWire(0);
175}
176
177template<class Impl>
178void
179DefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
180{
181 fetchQueue = fq_ptr;
182
183 // Setup wire to read information from fetch queue.
184 fromFetch = fetchQueue->getWire(-fetchToDecodeDelay);
185}
186
187template<class Impl>
188void
189DefaultDecode<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr)
190{
191 activeThreads = at_ptr;
192}
193
194template <class Impl>
195void
196DefaultDecode<Impl>::drainSanityCheck() const
197{
198 for (ThreadID tid = 0; tid < numThreads; ++tid) {
199 assert(insts[tid].empty());
200 assert(skidBuffer[tid].empty());
201 }
202}
203
204template<class Impl>
205bool
206DefaultDecode<Impl>::checkStall(ThreadID tid) const
207{
208 bool ret_val = false;
209
210 if (stalls[tid].rename) {
211 DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid);
212 ret_val = true;
213 } else if (stalls[tid].iew) {
214 DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid);
215 ret_val = true;
216 } else if (stalls[tid].commit) {
217 DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid);
218 ret_val = true;
219 }
220
221 return ret_val;
222}
223
224template<class Impl>
225inline bool
226DefaultDecode<Impl>::fetchInstsValid()
227{
228 return fromFetch->size > 0;
229}
230
231template<class Impl>
232bool
233DefaultDecode<Impl>::block(ThreadID tid)
234{
235 DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid);
236
237 // Add the current inputs to the skid buffer so they can be
238 // reprocessed when this stage unblocks.
239 skidInsert(tid);
240
241 // If the decode status is blocked or unblocking then decode has not yet
242 // signalled fetch to unblock. In that case, there is no need to tell
243 // fetch to block.
244 if (decodeStatus[tid] != Blocked) {
245 // Set the status to Blocked.
246 decodeStatus[tid] = Blocked;
247
248 if (toFetch->decodeUnblock[tid]) {
249 toFetch->decodeUnblock[tid] = false;
250 } else {
251 toFetch->decodeBlock[tid] = true;
252 wroteToTimeBuffer = true;
253 }
254
255 return true;
256 }
257
258 return false;
259}
260
261template<class Impl>
262bool
263DefaultDecode<Impl>::unblock(ThreadID tid)
264{
265 // Decode is done unblocking only if the skid buffer is empty.
266 if (skidBuffer[tid].empty()) {
267 DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid);
268 toFetch->decodeUnblock[tid] = true;
269 wroteToTimeBuffer = true;
270
271 decodeStatus[tid] = Running;
272 return true;
273 }
274
275 DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid);
276
277 return false;
278}
279
280template<class Impl>
281void
282DefaultDecode<Impl>::squash(DynInstPtr &inst, ThreadID tid)
283{
284 DPRINTF(Decode, "[tid:%i]: [sn:%i] Squashing due to incorrect branch "
285 "prediction detected at decode.\n", tid, inst->seqNum);
286
287 // Send back mispredict information.
288 toFetch->decodeInfo[tid].branchMispredict = true;
289 toFetch->decodeInfo[tid].predIncorrect = true;
290 toFetch->decodeInfo[tid].mispredictInst = inst;
291 toFetch->decodeInfo[tid].squash = true;
292 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
293 toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
294 toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching();
295 toFetch->decodeInfo[tid].squashInst = inst;
296 if (toFetch->decodeInfo[tid].mispredictInst->isUncondCtrl()) {
297 toFetch->decodeInfo[tid].branchTaken = true;
298 }
299
300 InstSeqNum squash_seq_num = inst->seqNum;
301
302 // Might have to tell fetch to unblock.
303 if (decodeStatus[tid] == Blocked ||
304 decodeStatus[tid] == Unblocking) {
305 toFetch->decodeUnblock[tid] = 1;
306 }
307
308 // Set status to squashing.
309 decodeStatus[tid] = Squashing;
310
311 for (int i=0; i<fromFetch->size; i++) {
312 if (fromFetch->insts[i]->threadNumber == tid &&
313 fromFetch->insts[i]->seqNum > squash_seq_num) {
314 fromFetch->insts[i]->setSquashed();
315 }
316 }
317
318 // Clear the instruction list and skid buffer in case they have any
319 // insts in them.
320 while (!insts[tid].empty()) {
321 insts[tid].pop();
322 }
323
324 while (!skidBuffer[tid].empty()) {
325 skidBuffer[tid].pop();
326 }
327
328 // Squash instructions up until this one
329 cpu->removeInstsUntil(squash_seq_num, tid);
330}
331
332template<class Impl>
333unsigned
334DefaultDecode<Impl>::squash(ThreadID tid)
335{
336 DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid);
337
338 if (decodeStatus[tid] == Blocked ||
339 decodeStatus[tid] == Unblocking) {
340 if (FullSystem) {
341 toFetch->decodeUnblock[tid] = 1;
342 } else {
343 // In syscall emulation, we can have both a block and a squash due
344 // to a syscall in the same cycle. This would cause both signals
345 // to be high. This shouldn't happen in full system.
346 // @todo: Determine if this still happens.
347 if (toFetch->decodeBlock[tid])
348 toFetch->decodeBlock[tid] = 0;
349 else
350 toFetch->decodeUnblock[tid] = 1;
351 }
352 }
353
354 // Set status to squashing.
355 decodeStatus[tid] = Squashing;
356
357 // Go through incoming instructions from fetch and squash them.
358 unsigned squash_count = 0;
359
360 for (int i=0; i<fromFetch->size; i++) {
361 if (fromFetch->insts[i]->threadNumber == tid) {
362 fromFetch->insts[i]->setSquashed();
363 squash_count++;
364 }
365 }
366
367 // Clear the instruction list and skid buffer in case they have any
368 // insts in them.
369 while (!insts[tid].empty()) {
370 insts[tid].pop();
371 }
372
373 while (!skidBuffer[tid].empty()) {
374 skidBuffer[tid].pop();
375 }
376
377 return squash_count;
378}
379
380template<class Impl>
381void
382DefaultDecode<Impl>::skidInsert(ThreadID tid)
383{
384 DynInstPtr inst = NULL;
385
386 while (!insts[tid].empty()) {
387 inst = insts[tid].front();
388
389 insts[tid].pop();
390
391 assert(tid == inst->threadNumber);
392
393 DPRINTF(Decode,"Inserting [sn:%lli] PC: %s into decode skidBuffer %i\n",
394 inst->seqNum, inst->pcState(), inst->threadNumber);
395
396 skidBuffer[tid].push(inst);
397 }
398
399 // @todo: Eventually need to enforce this by not letting a thread
400 // fetch past its skidbuffer
401 assert(skidBuffer[tid].size() <= skidBufferMax);
402}
403
404template<class Impl>
405bool
406DefaultDecode<Impl>::skidsEmpty()
407{
408 list<ThreadID>::iterator threads = activeThreads->begin();
409 list<ThreadID>::iterator end = activeThreads->end();
410
411 while (threads != end) {
412 ThreadID tid = *threads++;
413 if (!skidBuffer[tid].empty())
414 return false;
415 }
416
417 return true;
418}
419
420template<class Impl>
421void
422DefaultDecode<Impl>::updateStatus()
423{
424 bool any_unblocking = false;
425
426 list<ThreadID>::iterator threads = activeThreads->begin();
427 list<ThreadID>::iterator end = activeThreads->end();
428
429 while (threads != end) {
430 ThreadID tid = *threads++;
431
432 if (decodeStatus[tid] == Unblocking) {
433 any_unblocking = true;
434 break;
435 }
436 }
437
438 // Decode will have activity if it's unblocking.
439 if (any_unblocking) {
440 if (_status == Inactive) {
441 _status = Active;
442
443 DPRINTF(Activity, "Activating stage.\n");
444
445 cpu->activateStage(O3CPU::DecodeIdx);
446 }
447 } else {
448 // If it's not unblocking, then decode will not have any internal
449 // activity. Switch it to inactive.
450 if (_status == Active) {
451 _status = Inactive;
452 DPRINTF(Activity, "Deactivating stage.\n");
453
454 cpu->deactivateStage(O3CPU::DecodeIdx);
455 }
456 }
457}
458
459template <class Impl>
460void
461DefaultDecode<Impl>::sortInsts()
462{
463 int insts_from_fetch = fromFetch->size;
464 for (int i = 0; i < insts_from_fetch; ++i) {
465 insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]);
466 }
467}
468
469template<class Impl>
470void
471DefaultDecode<Impl>::readStallSignals(ThreadID tid)
472{
473 if (fromRename->renameBlock[tid]) {
474 stalls[tid].rename = true;
475 }
476
477 if (fromRename->renameUnblock[tid]) {
478 assert(stalls[tid].rename);
479 stalls[tid].rename = false;
480 }
481
482 if (fromIEW->iewBlock[tid]) {
483 stalls[tid].iew = true;
484 }
485
486 if (fromIEW->iewUnblock[tid]) {
487 assert(stalls[tid].iew);
488 stalls[tid].iew = false;
489 }
490
491 if (fromCommit->commitBlock[tid]) {
492 stalls[tid].commit = true;
493 }
494
495 if (fromCommit->commitUnblock[tid]) {
496 assert(stalls[tid].commit);
497 stalls[tid].commit = false;
498 }
499}
500
501template <class Impl>
502bool
503DefaultDecode<Impl>::checkSignalsAndUpdate(ThreadID tid)
504{
505 // Check if there's a squash signal, squash if there is.
506 // Check stall signals, block if necessary.
507 // If status was blocked
508 // Check if stall conditions have passed
509 // if so then go to unblocking
510 // If status was Squashing
511 // check if squashing is not high. Switch to running this cycle.
512
513 // Update the per thread stall statuses.
514 readStallSignals(tid);
515
516 // Check squash signals from commit.
517 if (fromCommit->commitInfo[tid].squash) {
518
519 DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash "
520 "from commit.\n", tid);
521
522 squash(tid);
523
524 return true;
525 }
526
527 // Check ROB squash signals from commit.
528 if (fromCommit->commitInfo[tid].robSquashing) {
529 DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid);
530
531 // Continue to squash.
532 decodeStatus[tid] = Squashing;
533
534 return true;
535 }
536
537 if (checkStall(tid)) {
538 return block(tid);
539 }
540
541 if (decodeStatus[tid] == Blocked) {
542 DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n",
543 tid);
544
545 decodeStatus[tid] = Unblocking;
546
547 unblock(tid);
548
549 return true;
550 }
551
552 if (decodeStatus[tid] == Squashing) {
553 // Switch status to running if decode isn't being told to block or
554 // squash this cycle.
555 DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n",
556 tid);
557
558 decodeStatus[tid] = Running;
559
560 return false;
561 }
562
563 // If we've reached this point, we have not gotten any signals that
564 // cause decode to change its status. Decode remains the same as before.
565 return false;
566}
567
568template<class Impl>
569void
570DefaultDecode<Impl>::tick()
571{
572 wroteToTimeBuffer = false;
573
574 bool status_change = false;
575
576 toRenameIndex = 0;
577
578 list<ThreadID>::iterator threads = activeThreads->begin();
579 list<ThreadID>::iterator end = activeThreads->end();
580
581 sortInsts();
582
583 //Check stall and squash signals.
584 while (threads != end) {
585 ThreadID tid = *threads++;
586
587 DPRINTF(Decode,"Processing [tid:%i]\n",tid);
588 status_change = checkSignalsAndUpdate(tid) || status_change;
589
590 decode(status_change, tid);
591 }
592
593 if (status_change) {
594 updateStatus();
595 }
596
597 if (wroteToTimeBuffer) {
598 DPRINTF(Activity, "Activity this cycle.\n");
599
600 cpu->activityThisCycle();
601 }
602}
603
604template<class Impl>
605void
606DefaultDecode<Impl>::decode(bool &status_change, ThreadID tid)
607{
608 // If status is Running or idle,
609 // call decodeInsts()
610 // If status is Unblocking,
611 // buffer any instructions coming from fetch
612 // continue trying to empty skid buffer
613 // check if stall conditions have passed
614
615 if (decodeStatus[tid] == Blocked) {
616 ++decodeBlockedCycles;
617 } else if (decodeStatus[tid] == Squashing) {
618 ++decodeSquashCycles;
619 }
620
621 // Decode should try to decode as many instructions as its bandwidth
622 // will allow, as long as it is not currently blocked.
623 if (decodeStatus[tid] == Running ||
624 decodeStatus[tid] == Idle) {
625 DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run "
626 "stage.\n",tid);
627
628 decodeInsts(tid);
629 } else if (decodeStatus[tid] == Unblocking) {
630 // Make sure that the skid buffer has something in it if the
631 // status is unblocking.
632 assert(!skidsEmpty());
633
634 // If the status was unblocking, then instructions from the skid
635 // buffer were used. Remove those instructions and handle
636 // the rest of unblocking.
637 decodeInsts(tid);
638
639 if (fetchInstsValid()) {
640 // Add the current inputs to the skid buffer so they can be
641 // reprocessed when this stage unblocks.
642 skidInsert(tid);
643 }
644
645 status_change = unblock(tid) || status_change;
646 }
647}
648
649template <class Impl>
650void
651DefaultDecode<Impl>::decodeInsts(ThreadID tid)
652{
653 // Instructions can come either from the skid buffer or the list of
654 // instructions coming from fetch, depending on decode's status.
655 int insts_available = decodeStatus[tid] == Unblocking ?
656 skidBuffer[tid].size() : insts[tid].size();
657
658 if (insts_available == 0) {
659 DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out"
660 " early.\n",tid);
661 // Should I change the status to idle?
662 ++decodeIdleCycles;
663 return;
664 } else if (decodeStatus[tid] == Unblocking) {
665 DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid "
666 "buffer.\n",tid);
667 ++decodeUnblockCycles;
668 } else if (decodeStatus[tid] == Running) {
669 ++decodeRunCycles;
670 }
671
672 DynInstPtr inst;
673
674 std::queue<DynInstPtr>
675 &insts_to_decode = decodeStatus[tid] == Unblocking ?
676 skidBuffer[tid] : insts[tid];
677
678 DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid);
679
680 while (insts_available > 0 && toRenameIndex < decodeWidth) {
681 assert(!insts_to_decode.empty());
682
683 inst = insts_to_decode.front();
684
685 insts_to_decode.pop();
686
687 DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with "
688 "PC %s\n", tid, inst->seqNum, inst->pcState());
689
690 if (inst->isSquashed()) {
691 DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %s is "
692 "squashed, skipping.\n",
693 tid, inst->seqNum, inst->pcState());
694
695 ++decodeSquashedInsts;
696
697 --insts_available;
698
699 continue;
700 }
701
702 // Also check if instructions have no source registers. Mark
703 // them as ready to issue at any time. Not sure if this check
704 // should exist here or at a later stage; however it doesn't matter
705 // too much for function correctness.
706 if (inst->numSrcRegs() == 0) {
707 inst->setCanIssue();
708 }
709
710 // This current instruction is valid, so add it into the decode
711 // queue. The next instruction may not be valid, so check to
712 // see if branches were predicted correctly.
713 toRename->insts[toRenameIndex] = inst;
714
715 ++(toRename->size);
716 ++toRenameIndex;
717 ++decodeDecodedInsts;
718 --insts_available;
719
720#if TRACING_ON
721 if (DTRACE(O3PipeView)) {
722 inst->decodeTick = curTick() - inst->fetchTick;
723 }
724#endif
725
726 // Ensure that if it was predicted as a branch, it really is a
727 // branch.
728 if (inst->readPredTaken() && !inst->isControl()) {
729 panic("Instruction predicted as a branch!");
730
731 ++decodeControlMispred;
732
733 // Might want to set some sort of boolean and just do
734 // a check at the end
735 squash(inst, inst->threadNumber);
736
737 break;
738 }
739
740 // Go ahead and compute any PC-relative branches.
741 if (inst->isDirectCtrl() && inst->isUncondCtrl()) {
742 ++decodeBranchResolved;
743
744 if (!(inst->branchTarget() == inst->readPredTarg())) {
745 ++decodeBranchMispred;
746
747 // Might want to set some sort of boolean and just do
748 // a check at the end
749 squash(inst, inst->threadNumber);
750 TheISA::PCState target = inst->branchTarget();
751
752 DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %s\n",
753 inst->seqNum, target);
754 //The micro pc after an instruction level branch should be 0
755 inst->setPredTarg(target);
756 break;
757 }
758 }
759 }
760
761 // If we didn't process all instructions, then we will need to block
762 // and put all those instructions into the skid buffer.
763 if (!insts_to_decode.empty()) {
764 block(tid);
765 }
766
767 // Record that decode has written to the time buffer for activity
768 // tracking.
769 if (toRenameIndex) {
770 wroteToTimeBuffer = true;
771 }
772}
773
774#endif//__CPU_O3_DECODE_IMPL_HH__