1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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419 // fetch past its skidbuffer
420 assert(skidBuffer[tid].size() <= skidBufferMax);
421}
422
423template<class Impl>
424bool
425DefaultDecode<Impl>::skidsEmpty()
426{
427 std::list<unsigned>::iterator threads = activeThreads->begin();
428 std::list<unsigned>::iterator end = activeThreads->end();
429
430 while (threads != end) {
431 unsigned tid = *threads++;
432 if (!skidBuffer[tid].empty())
433 return false;
434 }
435
436 return true;
437}
438
439template<class Impl>
440void
441DefaultDecode<Impl>::updateStatus()
442{
443 bool any_unblocking = false;
444
445 std::list<unsigned>::iterator threads = activeThreads->begin();
446 std::list<unsigned>::iterator end = activeThreads->end();
447
448 while (threads != end) {
449 unsigned tid = *threads++;
450
451 if (decodeStatus[tid] == Unblocking) {
452 any_unblocking = true;
453 break;
454 }
455 }
456

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593DefaultDecode<Impl>::tick()
594{
595 wroteToTimeBuffer = false;
596
597 bool status_change = false;
598
599 toRenameIndex = 0;
600
601 std::list<unsigned>::iterator threads = activeThreads->begin();
602 std::list<unsigned>::iterator end = activeThreads->end();
603
604 sortInsts();
605
606 //Check stall and squash signals.
607 while (threads != end) {
608 unsigned tid = *threads++;
609
610 DPRINTF(Decode,"Processing [tid:%i]\n",tid);
611 status_change = checkSignalsAndUpdate(tid) || status_change;
612
613 decode(status_change, tid);
614 }
615
616 if (status_change) {

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738
739 ++(toRename->size);
740 ++toRenameIndex;
741 ++decodeDecodedInsts;
742 --insts_available;
743
744 // Ensure that if it was predicted as a branch, it really is a
745 // branch.
746 if (inst->predTaken() && !inst->isControl()) {
747 DPRINTF(Decode, "PredPC : %#x != NextPC: %#x\n",inst->predPC,
748 inst->nextPC + 4);
749
750 panic("Instruction predicted as a branch!");
751
752 ++decodeControlMispred;
753
754 // Might want to set some sort of boolean and just do
755 // a check at the end
756 squash(inst, inst->threadNumber);
757
758 break;
759 }
760
761 // Go ahead and compute any PC-relative branches.
762 if (inst->isDirectCtrl() && inst->isUncondCtrl()) {
763 ++decodeBranchResolved;
764
765 if (inst->branchTarget() != inst->readPredTarg()) {
766 ++decodeBranchMispred;
767
768 // Might want to set some sort of boolean and just do
769 // a check at the end
770#if !ISA_HAS_DELAY_SLOT
771 squash(inst, inst->threadNumber);
772 inst->setPredTarg(inst->branchTarget());
773 break;
774#else
775 // If mispredicted as taken, then ignore delay slot
776 // instruction... else keep delay slot and squash
777 // after it is sent to rename
778 if (inst->predTaken() && inst->isCondDelaySlot()) {
779 DPRINTF(Decode, "[tid:%i]: Conditional delay slot inst."
780 "[sn:%i] PC %#x mispredicted as taken.\n", tid,
781 inst->seqNum, inst->PC);
782 bdelayDoneSeqNum[tid] = inst->seqNum;
783 squash(inst, inst->threadNumber);
784 inst->setPredTarg(inst->branchTarget());
785 break;
786 } else {
787 DPRINTF(Decode, "[tid:%i]: Misprediction detected at "
788 "[sn:%i] PC %#x, will squash after delay slot "
789 "inst. is sent to Rename\n",
790 tid, inst->seqNum, inst->PC);
791 bdelayDoneSeqNum[tid] = inst->seqNum + 1;
792 squashAfterDelaySlot[tid] = true;
793 squashInst[tid] = inst;
794 continue;
795 }
796#endif
797 }
798 }
799
800 if (squashAfterDelaySlot[tid]) {
801 assert(!inst->isSquashed());
802 squash(squashInst[tid], squashInst[tid]->threadNumber);
803 squashInst[tid]->setPredTarg(squashInst[tid]->branchTarget());
804 assert(!inst->isSquashed());
805 break;
806 }
807 }
808
809 // If we didn't process all instructions, then we will need to block
810 // and put all those instructions into the skid buffer.
811 if (!insts_to_decode.empty()) {
812 block(tid);
813 }
814
815 // Record that decode has written to the time buffer for activity
816 // tracking.
817 if (toRenameIndex) {
818 wroteToTimeBuffer = true;
819 }
820}