1/*
2 * Copyright (c) 2012, 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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90{
91 _status = Inactive;
92
93 // Setup status, make sure stall signals are clear.
94 for (ThreadID tid = 0; tid < numThreads; ++tid) {
95 decodeStatus[tid] = Idle;
96
97 stalls[tid].rename = false;
98 }
99}
100
101template <class Impl>
102std::string
103DefaultDecode<Impl>::name() const
104{
105 return cpu->name() + ".decode";

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199DefaultDecode<Impl>::drainSanityCheck() const
200{
201 for (ThreadID tid = 0; tid < numThreads; ++tid) {
202 assert(insts[tid].empty());
203 assert(skidBuffer[tid].empty());
204 }
205}
206
207template <class Impl>
208bool
209DefaultDecode<Impl>::isDrained() const
210{
211 for (ThreadID tid = 0; tid < numThreads; ++tid) {
212 if (!insts[tid].empty() || !skidBuffer[tid].empty())
213 return false;
214 }
215 return true;
216}
217
218template<class Impl>
219bool
220DefaultDecode<Impl>::checkStall(ThreadID tid) const
221{
222 bool ret_val = false;
223
224 if (stalls[tid].rename) {
225 DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid);
226 ret_val = true;
227 }
228
229 return ret_val;
230}
231
232template<class Impl>
233inline bool
234DefaultDecode<Impl>::fetchInstsValid()

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393
394 while (!insts[tid].empty()) {
395 inst = insts[tid].front();
396
397 insts[tid].pop();
398
399 assert(tid == inst->threadNumber);
400
401 skidBuffer[tid].push(inst);
402
403 DPRINTF(Decode,"Inserting [tid:%d][sn:%lli] PC: %s into decode skidBuffer %i\n",
404 inst->threadNumber, inst->seqNum, inst->pcState(), skidBuffer[tid].size());
405 }
406
407 // @todo: Eventually need to enforce this by not letting a thread
408 // fetch past its skidbuffer
409 assert(skidBuffer[tid].size() <= skidBufferMax);
410}
411
412template<class Impl>

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481 if (fromRename->renameBlock[tid]) {
482 stalls[tid].rename = true;
483 }
484
485 if (fromRename->renameUnblock[tid]) {
486 assert(stalls[tid].rename);
487 stalls[tid].rename = false;
488 }
489}
490
491template <class Impl>
492bool
493DefaultDecode<Impl>::checkSignalsAndUpdate(ThreadID tid)
494{
495 // Check if there's a squash signal, squash if there is.
496 // Check stall signals, block if necessary.

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509 DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash "
510 "from commit.\n", tid);
511
512 squash(tid);
513
514 return true;
515 }
516
517 if (checkStall(tid)) {
518 return block(tid);
519 }
520
521 if (decodeStatus[tid] == Blocked) {
522 DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n",
523 tid);
524

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