decode.hh (2654:9559cfa91b9d) | decode.hh (2665:a124942bacb8) |
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1/* | 1/* |
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan | 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan |
3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the --- 8 unchanged lines hidden (view full) --- 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the --- 8 unchanged lines hidden (view full) --- 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 * 28 * Authors: Kevin Lim |
|
27 */ 28 | 29 */ 30 |
29#ifndef __CPU_O3_DECODE_HH__ 30#define __CPU_O3_DECODE_HH__ | 31#ifndef __CPU_O3_CPU_SIMPLE_DECODE_HH__ 32#define __CPU_O3_CPU_SIMPLE_DECODE_HH__ |
31 32#include <queue> 33 34#include "base/statistics.hh" 35#include "base/timebuf.hh" 36 | 33 34#include <queue> 35 36#include "base/statistics.hh" 37#include "base/timebuf.hh" 38 |
37/** 38 * DefaultDecode class handles both single threaded and SMT 39 * decode. Its width is specified by the parameters; each cycles it 40 * tries to decode that many instructions. Because instructions are 41 * actually decoded when the StaticInst is created, this stage does 42 * not do much other than check any PC-relative branches. 43 */ | |
44template<class Impl> | 39template<class Impl> |
45class DefaultDecode | 40class SimpleDecode |
46{ 47 private: 48 // Typedefs from the Impl. 49 typedef typename Impl::FullCPU FullCPU; 50 typedef typename Impl::DynInstPtr DynInstPtr; 51 typedef typename Impl::Params Params; 52 typedef typename Impl::CPUPol CPUPol; 53 54 // Typedefs from the CPU policy. 55 typedef typename CPUPol::FetchStruct FetchStruct; 56 typedef typename CPUPol::DecodeStruct DecodeStruct; 57 typedef typename CPUPol::TimeStruct TimeStruct; 58 59 public: | 41{ 42 private: 43 // Typedefs from the Impl. 44 typedef typename Impl::FullCPU FullCPU; 45 typedef typename Impl::DynInstPtr DynInstPtr; 46 typedef typename Impl::Params Params; 47 typedef typename Impl::CPUPol CPUPol; 48 49 // Typedefs from the CPU policy. 50 typedef typename CPUPol::FetchStruct FetchStruct; 51 typedef typename CPUPol::DecodeStruct DecodeStruct; 52 typedef typename CPUPol::TimeStruct TimeStruct; 53 54 public: |
60 /** Overall decode stage status. Used to determine if the CPU can 61 * deschedule itself due to a lack of activity. 62 */ 63 enum DecodeStatus { 64 Active, 65 Inactive 66 }; 67 68 /** Individual thread status. */ 69 enum ThreadStatus { | 55 // The only time decode will become blocked is if dispatch becomes 56 // blocked, which means IQ or ROB is probably full. 57 enum Status { |
70 Running, 71 Idle, | 58 Running, 59 Idle, |
72 StartSquash, | |
73 Squashing, 74 Blocked, 75 Unblocking 76 }; 77 78 private: | 60 Squashing, 61 Blocked, 62 Unblocking 63 }; 64 65 private: |
79 /** Decode status. */ 80 DecodeStatus _status; | 66 // May eventually need statuses on a per thread basis. 67 Status _status; |
81 | 68 |
82 /** Per-thread status. */ 83 ThreadStatus decodeStatus[Impl::MaxThreads]; 84 | |
85 public: | 69 public: |
86 /** DefaultDecode constructor. */ 87 DefaultDecode(Params *params); | 70 SimpleDecode(Params ¶ms); |
88 | 71 |
89 /** Returns the name of decode. */ 90 std::string name() const; 91 92 /** Registers statistics. */ | |
93 void regStats(); 94 | 72 void regStats(); 73 |
95 /** Sets CPU pointer. */ | |
96 void setCPU(FullCPU *cpu_ptr); 97 | 74 void setCPU(FullCPU *cpu_ptr); 75 |
98 /** Sets the main backwards communication time buffer pointer. */ | |
99 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 100 | 76 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 77 |
101 /** Sets pointer to time buffer used to communicate to the next stage. */ | |
102 void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr); 103 | 78 void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr); 79 |
104 /** Sets pointer to time buffer coming from fetch. */ | |
105 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 106 | 80 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 81 |
107 /** Sets pointer to list of active threads. */ 108 void setActiveThreads(std::list<unsigned> *at_ptr); 109 110 void switchOut(); 111 112 void takeOverFrom(); 113 /** Ticks decode, processing all input signals and decoding as many 114 * instructions as possible. 115 */ | |
116 void tick(); 117 | 82 void tick(); 83 |
118 /** Determines what to do based on decode's current status. 119 * @param status_change decode() sets this variable if there was a status 120 * change (ie switching from from blocking to unblocking). 121 * @param tid Thread id to decode instructions from. 122 */ 123 void decode(bool &status_change, unsigned tid); | 84 void decode(); |
124 | 85 |
125 /** Processes instructions from fetch and passes them on to rename. 126 * Decoding of instructions actually happens when they are created in 127 * fetch, so this function mostly checks if PC-relative branches are 128 * correct. 129 */ 130 void decodeInsts(unsigned tid); 131 | |
132 private: | 86 private: |
133 /** Inserts a thread's instructions into the skid buffer, to be decoded 134 * once decode unblocks. 135 */ 136 void skidInsert(unsigned tid); 137 138 /** Returns if all of the skid buffers are empty. */ 139 bool skidsEmpty(); 140 141 /** Updates overall decode status based on all of the threads' statuses. */ 142 void updateStatus(); 143 144 /** Separates instructions from fetch into individual lists of instructions 145 * sorted by thread. 146 */ 147 void sortInsts(); 148 149 /** Reads all stall signals from the backwards communication timebuffer. */ 150 void readStallSignals(unsigned tid); 151 152 /** Checks all input signals and updates decode's status appropriately. */ 153 bool checkSignalsAndUpdate(unsigned tid); 154 155 /** Checks all stall signals, and returns if any are true. */ 156 bool checkStall(unsigned tid) const; 157 158 /** Returns if there any instructions from fetch on this cycle. */ | |
159 inline bool fetchInstsValid(); 160 | 87 inline bool fetchInstsValid(); 88 |
161 /** Switches decode to blocking, and signals back that decode has 162 * become blocked. 163 * @return Returns true if there is a status change. 164 */ 165 bool block(unsigned tid); | 89 void block(); |
166 | 90 |
167 /** Switches decode to unblocking if the skid buffer is empty, and 168 * signals back that decode has unblocked. 169 * @return Returns true if there is a status change. 170 */ 171 bool unblock(unsigned tid); | 91 inline void unblock(); |
172 | 92 |
173 /** Squashes if there is a PC-relative branch that was predicted 174 * incorrectly. Sends squash information back to fetch. 175 */ 176 void squash(DynInstPtr &inst, unsigned tid); | 93 void squash(DynInstPtr &inst); |
177 178 public: | 94 95 public: |
179 /** Squashes due to commit signalling a squash. Changes status to 180 * squashing and clears block/unblock signals as needed. 181 */ 182 unsigned squash(unsigned tid); | 96 // Might want to make squash a friend function. 97 void squash(); |
183 184 private: 185 // Interfaces to objects outside of decode. 186 /** CPU interface. */ 187 FullCPU *cpu; 188 189 /** Time buffer interface. */ 190 TimeBuffer<TimeStruct> *timeBuffer; --- 18 unchanged lines hidden (view full) --- 209 typename TimeBuffer<DecodeStruct>::wire toRename; 210 211 /** Fetch instruction queue interface. */ 212 TimeBuffer<FetchStruct> *fetchQueue; 213 214 /** Wire to get fetch's output from fetch queue. */ 215 typename TimeBuffer<FetchStruct>::wire fromFetch; 216 | 98 99 private: 100 // Interfaces to objects outside of decode. 101 /** CPU interface. */ 102 FullCPU *cpu; 103 104 /** Time buffer interface. */ 105 TimeBuffer<TimeStruct> *timeBuffer; --- 18 unchanged lines hidden (view full) --- 124 typename TimeBuffer<DecodeStruct>::wire toRename; 125 126 /** Fetch instruction queue interface. */ 127 TimeBuffer<FetchStruct> *fetchQueue; 128 129 /** Wire to get fetch's output from fetch queue. */ 130 typename TimeBuffer<FetchStruct>::wire fromFetch; 131 |
217 /** Queue of all instructions coming from fetch this cycle. */ 218 std::queue<DynInstPtr> insts[Impl::MaxThreads]; 219 | |
220 /** Skid buffer between fetch and decode. */ | 132 /** Skid buffer between fetch and decode. */ |
221 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads]; | 133 std::queue<FetchStruct> skidBuffer; |
222 | 134 |
223 /** Variable that tracks if decode has written to the time buffer this 224 * cycle. Used to tell CPU if there is activity this cycle. 225 */ 226 bool wroteToTimeBuffer; 227 228 /** Source of possible stalls. */ 229 struct Stalls { 230 bool rename; 231 bool iew; 232 bool commit; 233 }; 234 235 /** Tracks which stages are telling decode to stall. */ 236 Stalls stalls[Impl::MaxThreads]; 237 | 135 //Consider making these unsigned to avoid any confusion. |
238 /** Rename to decode delay, in ticks. */ 239 unsigned renameToDecodeDelay; 240 241 /** IEW to decode delay, in ticks. */ 242 unsigned iewToDecodeDelay; 243 244 /** Commit to decode delay, in ticks. */ 245 unsigned commitToDecodeDelay; 246 247 /** Fetch to decode delay, in ticks. */ 248 unsigned fetchToDecodeDelay; 249 250 /** The width of decode, in instructions. */ 251 unsigned decodeWidth; 252 | 136 /** Rename to decode delay, in ticks. */ 137 unsigned renameToDecodeDelay; 138 139 /** IEW to decode delay, in ticks. */ 140 unsigned iewToDecodeDelay; 141 142 /** Commit to decode delay, in ticks. */ 143 unsigned commitToDecodeDelay; 144 145 /** Fetch to decode delay, in ticks. */ 146 unsigned fetchToDecodeDelay; 147 148 /** The width of decode, in instructions. */ 149 unsigned decodeWidth; 150 |
253 /** Index of instructions being sent to rename. */ 254 unsigned toRenameIndex; | 151 /** The instruction that decode is currently on. It needs to have 152 * persistent state so that when a stall occurs in the middle of a 153 * group of instructions, it can restart at the proper instruction. 154 */ 155 unsigned numInst; |
255 | 156 |
256 /** number of Active Threads*/ 257 unsigned numThreads; 258 259 /** List of active thread ids */ 260 std::list<unsigned> *activeThreads; 261 262 /** Number of branches in flight. */ 263 unsigned branchCount[Impl::MaxThreads]; 264 265 /** Maximum size of the skid buffer. */ 266 unsigned skidBufferMax; 267 268 /** Stat for total number of idle cycles. */ | |
269 Stats::Scalar<> decodeIdleCycles; | 157 Stats::Scalar<> decodeIdleCycles; |
270 /** Stat for total number of blocked cycles. */ | |
271 Stats::Scalar<> decodeBlockedCycles; | 158 Stats::Scalar<> decodeBlockedCycles; |
272 /** Stat for total number of normal running cycles. */ 273 Stats::Scalar<> decodeRunCycles; 274 /** Stat for total number of unblocking cycles. */ | |
275 Stats::Scalar<> decodeUnblockCycles; | 159 Stats::Scalar<> decodeUnblockCycles; |
276 /** Stat for total number of squashing cycles. */ | |
277 Stats::Scalar<> decodeSquashCycles; | 160 Stats::Scalar<> decodeSquashCycles; |
278 /** Stat for number of times a branch is resolved at decode. */ 279 Stats::Scalar<> decodeBranchResolved; 280 /** Stat for number of times a branch mispredict is detected. */ | |
281 Stats::Scalar<> decodeBranchMispred; | 161 Stats::Scalar<> decodeBranchMispred; |
282 /** Stat for number of times decode detected a non-control instruction 283 * incorrectly predicted as a branch. 284 */ | |
285 Stats::Scalar<> decodeControlMispred; | 162 Stats::Scalar<> decodeControlMispred; |
286 /** Stat for total number of decoded instructions. */ | |
287 Stats::Scalar<> decodeDecodedInsts; | 163 Stats::Scalar<> decodeDecodedInsts; |
288 /** Stat for total number of squashed instructions. */ | |
289 Stats::Scalar<> decodeSquashedInsts; 290}; 291 | 164 Stats::Scalar<> decodeSquashedInsts; 165}; 166 |
292#endif // __CPU_O3_DECODE_HH__ | 167#endif // __CPU_O3_CPU_SIMPLE_DECODE_HH__ |