1/*
| 1/*
|
| 2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
|
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_O3_DECODE_HH__
32#define __CPU_O3_DECODE_HH__
33
34#include <queue>
35
36#include "base/statistics.hh"
37#include "cpu/timebuf.hh"
38
39struct DerivO3CPUParams;
40
41/**
42 * DefaultDecode class handles both single threaded and SMT
43 * decode. Its width is specified by the parameters; each cycles it
44 * tries to decode that many instructions. Because instructions are
45 * actually decoded when the StaticInst is created, this stage does
46 * not do much other than check any PC-relative branches.
47 */
48template<class Impl>
49class DefaultDecode
50{
51 private:
52 // Typedefs from the Impl.
53 typedef typename Impl::O3CPU O3CPU;
54 typedef typename Impl::DynInstPtr DynInstPtr;
55 typedef typename Impl::CPUPol CPUPol;
56
57 // Typedefs from the CPU policy.
58 typedef typename CPUPol::FetchStruct FetchStruct;
59 typedef typename CPUPol::DecodeStruct DecodeStruct;
60 typedef typename CPUPol::TimeStruct TimeStruct;
61
62 public:
63 /** Overall decode stage status. Used to determine if the CPU can
64 * deschedule itself due to a lack of activity.
65 */
66 enum DecodeStatus {
67 Active,
68 Inactive
69 };
70
71 /** Individual thread status. */
72 enum ThreadStatus {
73 Running,
74 Idle,
75 StartSquash,
76 Squashing,
77 Blocked,
78 Unblocking
79 };
80
81 private:
82 /** Decode status. */
83 DecodeStatus _status;
84
85 /** Per-thread status. */
86 ThreadStatus decodeStatus[Impl::MaxThreads];
87
88 public:
89 /** DefaultDecode constructor. */
90 DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params);
91
| 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_O3_DECODE_HH__
44#define __CPU_O3_DECODE_HH__
45
46#include <queue>
47
48#include "base/statistics.hh"
49#include "cpu/timebuf.hh"
50
51struct DerivO3CPUParams;
52
53/**
54 * DefaultDecode class handles both single threaded and SMT
55 * decode. Its width is specified by the parameters; each cycles it
56 * tries to decode that many instructions. Because instructions are
57 * actually decoded when the StaticInst is created, this stage does
58 * not do much other than check any PC-relative branches.
59 */
60template<class Impl>
61class DefaultDecode
62{
63 private:
64 // Typedefs from the Impl.
65 typedef typename Impl::O3CPU O3CPU;
66 typedef typename Impl::DynInstPtr DynInstPtr;
67 typedef typename Impl::CPUPol CPUPol;
68
69 // Typedefs from the CPU policy.
70 typedef typename CPUPol::FetchStruct FetchStruct;
71 typedef typename CPUPol::DecodeStruct DecodeStruct;
72 typedef typename CPUPol::TimeStruct TimeStruct;
73
74 public:
75 /** Overall decode stage status. Used to determine if the CPU can
76 * deschedule itself due to a lack of activity.
77 */
78 enum DecodeStatus {
79 Active,
80 Inactive
81 };
82
83 /** Individual thread status. */
84 enum ThreadStatus {
85 Running,
86 Idle,
87 StartSquash,
88 Squashing,
89 Blocked,
90 Unblocking
91 };
92
93 private:
94 /** Decode status. */
95 DecodeStatus _status;
96
97 /** Per-thread status. */
98 ThreadStatus decodeStatus[Impl::MaxThreads];
99
100 public:
101 /** DefaultDecode constructor. */
102 DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params);
103
|
| 104 void startupStage();
105 void resetStage();
106
|
92 /** Returns the name of decode. */
93 std::string name() const;
94
95 /** Registers statistics. */
96 void regStats();
97
98 /** Sets the main backwards communication time buffer pointer. */
99 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
100
101 /** Sets pointer to time buffer used to communicate to the next stage. */
102 void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
103
104 /** Sets pointer to time buffer coming from fetch. */
105 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
106
107 /** Sets pointer to list of active threads. */
108 void setActiveThreads(std::list<ThreadID> *at_ptr);
109
| 107 /** Returns the name of decode. */
108 std::string name() const;
109
110 /** Registers statistics. */
111 void regStats();
112
113 /** Sets the main backwards communication time buffer pointer. */
114 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
115
116 /** Sets pointer to time buffer used to communicate to the next stage. */
117 void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
118
119 /** Sets pointer to time buffer coming from fetch. */
120 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
121
122 /** Sets pointer to list of active threads. */
123 void setActiveThreads(std::list<ThreadID> *at_ptr);
124
|
110 /** Drains the decode stage. */
111 bool drain();
| 125 /** Perform sanity checks after a drain. */
126 void drainSanityCheck() const;
|
112
| 127
|
113 /** Resumes execution after a drain. */
114 void resume() { }
| 128 /** Has the stage drained? */
129 bool isDrained() const { return true; }
|
115
| 130
|
116 /** Switches out the decode stage. */
117 void switchOut() { }
118
| |
119 /** Takes over from another CPU's thread. */
| 131 /** Takes over from another CPU's thread. */
|
120 void takeOverFrom();
| 132 void takeOverFrom() { resetStage(); }
|
121
122 /** Ticks decode, processing all input signals and decoding as many
123 * instructions as possible.
124 */
125 void tick();
126
127 /** Determines what to do based on decode's current status.
128 * @param status_change decode() sets this variable if there was a status
129 * change (ie switching from from blocking to unblocking).
130 * @param tid Thread id to decode instructions from.
131 */
132 void decode(bool &status_change, ThreadID tid);
133
134 /** Processes instructions from fetch and passes them on to rename.
135 * Decoding of instructions actually happens when they are created in
136 * fetch, so this function mostly checks if PC-relative branches are
137 * correct.
138 */
139 void decodeInsts(ThreadID tid);
140
141 private:
142 /** Inserts a thread's instructions into the skid buffer, to be decoded
143 * once decode unblocks.
144 */
145 void skidInsert(ThreadID tid);
146
147 /** Returns if all of the skid buffers are empty. */
148 bool skidsEmpty();
149
150 /** Updates overall decode status based on all of the threads' statuses. */
151 void updateStatus();
152
153 /** Separates instructions from fetch into individual lists of instructions
154 * sorted by thread.
155 */
156 void sortInsts();
157
158 /** Reads all stall signals from the backwards communication timebuffer. */
159 void readStallSignals(ThreadID tid);
160
161 /** Checks all input signals and updates decode's status appropriately. */
162 bool checkSignalsAndUpdate(ThreadID tid);
163
164 /** Checks all stall signals, and returns if any are true. */
165 bool checkStall(ThreadID tid) const;
166
167 /** Returns if there any instructions from fetch on this cycle. */
168 inline bool fetchInstsValid();
169
170 /** Switches decode to blocking, and signals back that decode has
171 * become blocked.
172 * @return Returns true if there is a status change.
173 */
174 bool block(ThreadID tid);
175
176 /** Switches decode to unblocking if the skid buffer is empty, and
177 * signals back that decode has unblocked.
178 * @return Returns true if there is a status change.
179 */
180 bool unblock(ThreadID tid);
181
182 /** Squashes if there is a PC-relative branch that was predicted
183 * incorrectly. Sends squash information back to fetch.
184 */
185 void squash(DynInstPtr &inst, ThreadID tid);
186
187 public:
188 /** Squashes due to commit signalling a squash. Changes status to
189 * squashing and clears block/unblock signals as needed.
190 */
191 unsigned squash(ThreadID tid);
192
193 private:
194 // Interfaces to objects outside of decode.
195 /** CPU interface. */
196 O3CPU *cpu;
197
198 /** Time buffer interface. */
199 TimeBuffer<TimeStruct> *timeBuffer;
200
201 /** Wire to get rename's output from backwards time buffer. */
202 typename TimeBuffer<TimeStruct>::wire fromRename;
203
204 /** Wire to get iew's information from backwards time buffer. */
205 typename TimeBuffer<TimeStruct>::wire fromIEW;
206
207 /** Wire to get commit's information from backwards time buffer. */
208 typename TimeBuffer<TimeStruct>::wire fromCommit;
209
210 /** Wire to write information heading to previous stages. */
211 // Might not be the best name as not only fetch will read it.
212 typename TimeBuffer<TimeStruct>::wire toFetch;
213
214 /** Decode instruction queue. */
215 TimeBuffer<DecodeStruct> *decodeQueue;
216
217 /** Wire used to write any information heading to rename. */
218 typename TimeBuffer<DecodeStruct>::wire toRename;
219
220 /** Fetch instruction queue interface. */
221 TimeBuffer<FetchStruct> *fetchQueue;
222
223 /** Wire to get fetch's output from fetch queue. */
224 typename TimeBuffer<FetchStruct>::wire fromFetch;
225
226 /** Queue of all instructions coming from fetch this cycle. */
227 std::queue<DynInstPtr> insts[Impl::MaxThreads];
228
229 /** Skid buffer between fetch and decode. */
230 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
231
232 /** Variable that tracks if decode has written to the time buffer this
233 * cycle. Used to tell CPU if there is activity this cycle.
234 */
235 bool wroteToTimeBuffer;
236
237 /** Source of possible stalls. */
238 struct Stalls {
239 bool rename;
240 bool iew;
241 bool commit;
242 };
243
244 /** Tracks which stages are telling decode to stall. */
245 Stalls stalls[Impl::MaxThreads];
246
247 /** Rename to decode delay. */
248 Cycles renameToDecodeDelay;
249
250 /** IEW to decode delay. */
251 Cycles iewToDecodeDelay;
252
253 /** Commit to decode delay. */
254 Cycles commitToDecodeDelay;
255
256 /** Fetch to decode delay. */
257 Cycles fetchToDecodeDelay;
258
259 /** The width of decode, in instructions. */
260 unsigned decodeWidth;
261
262 /** Index of instructions being sent to rename. */
263 unsigned toRenameIndex;
264
265 /** number of Active Threads*/
266 ThreadID numThreads;
267
268 /** List of active thread ids */
269 std::list<ThreadID> *activeThreads;
270
| 133
134 /** Ticks decode, processing all input signals and decoding as many
135 * instructions as possible.
136 */
137 void tick();
138
139 /** Determines what to do based on decode's current status.
140 * @param status_change decode() sets this variable if there was a status
141 * change (ie switching from from blocking to unblocking).
142 * @param tid Thread id to decode instructions from.
143 */
144 void decode(bool &status_change, ThreadID tid);
145
146 /** Processes instructions from fetch and passes them on to rename.
147 * Decoding of instructions actually happens when they are created in
148 * fetch, so this function mostly checks if PC-relative branches are
149 * correct.
150 */
151 void decodeInsts(ThreadID tid);
152
153 private:
154 /** Inserts a thread's instructions into the skid buffer, to be decoded
155 * once decode unblocks.
156 */
157 void skidInsert(ThreadID tid);
158
159 /** Returns if all of the skid buffers are empty. */
160 bool skidsEmpty();
161
162 /** Updates overall decode status based on all of the threads' statuses. */
163 void updateStatus();
164
165 /** Separates instructions from fetch into individual lists of instructions
166 * sorted by thread.
167 */
168 void sortInsts();
169
170 /** Reads all stall signals from the backwards communication timebuffer. */
171 void readStallSignals(ThreadID tid);
172
173 /** Checks all input signals and updates decode's status appropriately. */
174 bool checkSignalsAndUpdate(ThreadID tid);
175
176 /** Checks all stall signals, and returns if any are true. */
177 bool checkStall(ThreadID tid) const;
178
179 /** Returns if there any instructions from fetch on this cycle. */
180 inline bool fetchInstsValid();
181
182 /** Switches decode to blocking, and signals back that decode has
183 * become blocked.
184 * @return Returns true if there is a status change.
185 */
186 bool block(ThreadID tid);
187
188 /** Switches decode to unblocking if the skid buffer is empty, and
189 * signals back that decode has unblocked.
190 * @return Returns true if there is a status change.
191 */
192 bool unblock(ThreadID tid);
193
194 /** Squashes if there is a PC-relative branch that was predicted
195 * incorrectly. Sends squash information back to fetch.
196 */
197 void squash(DynInstPtr &inst, ThreadID tid);
198
199 public:
200 /** Squashes due to commit signalling a squash. Changes status to
201 * squashing and clears block/unblock signals as needed.
202 */
203 unsigned squash(ThreadID tid);
204
205 private:
206 // Interfaces to objects outside of decode.
207 /** CPU interface. */
208 O3CPU *cpu;
209
210 /** Time buffer interface. */
211 TimeBuffer<TimeStruct> *timeBuffer;
212
213 /** Wire to get rename's output from backwards time buffer. */
214 typename TimeBuffer<TimeStruct>::wire fromRename;
215
216 /** Wire to get iew's information from backwards time buffer. */
217 typename TimeBuffer<TimeStruct>::wire fromIEW;
218
219 /** Wire to get commit's information from backwards time buffer. */
220 typename TimeBuffer<TimeStruct>::wire fromCommit;
221
222 /** Wire to write information heading to previous stages. */
223 // Might not be the best name as not only fetch will read it.
224 typename TimeBuffer<TimeStruct>::wire toFetch;
225
226 /** Decode instruction queue. */
227 TimeBuffer<DecodeStruct> *decodeQueue;
228
229 /** Wire used to write any information heading to rename. */
230 typename TimeBuffer<DecodeStruct>::wire toRename;
231
232 /** Fetch instruction queue interface. */
233 TimeBuffer<FetchStruct> *fetchQueue;
234
235 /** Wire to get fetch's output from fetch queue. */
236 typename TimeBuffer<FetchStruct>::wire fromFetch;
237
238 /** Queue of all instructions coming from fetch this cycle. */
239 std::queue<DynInstPtr> insts[Impl::MaxThreads];
240
241 /** Skid buffer between fetch and decode. */
242 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
243
244 /** Variable that tracks if decode has written to the time buffer this
245 * cycle. Used to tell CPU if there is activity this cycle.
246 */
247 bool wroteToTimeBuffer;
248
249 /** Source of possible stalls. */
250 struct Stalls {
251 bool rename;
252 bool iew;
253 bool commit;
254 };
255
256 /** Tracks which stages are telling decode to stall. */
257 Stalls stalls[Impl::MaxThreads];
258
259 /** Rename to decode delay. */
260 Cycles renameToDecodeDelay;
261
262 /** IEW to decode delay. */
263 Cycles iewToDecodeDelay;
264
265 /** Commit to decode delay. */
266 Cycles commitToDecodeDelay;
267
268 /** Fetch to decode delay. */
269 Cycles fetchToDecodeDelay;
270
271 /** The width of decode, in instructions. */
272 unsigned decodeWidth;
273
274 /** Index of instructions being sent to rename. */
275 unsigned toRenameIndex;
276
277 /** number of Active Threads*/
278 ThreadID numThreads;
279
280 /** List of active thread ids */
281 std::list<ThreadID> *activeThreads;
282
|
271 /** Number of branches in flight. */
272 unsigned branchCount[Impl::MaxThreads];
273
| |
274 /** Maximum size of the skid buffer. */
275 unsigned skidBufferMax;
276
277 /** SeqNum of Squashing Branch Delay Instruction (used for MIPS)*/
278 Addr bdelayDoneSeqNum[Impl::MaxThreads];
279
280 /** Instruction used for squashing branch (used for MIPS)*/
281 DynInstPtr squashInst[Impl::MaxThreads];
282
283 /** Tells when their is a pending delay slot inst. to send
284 * to rename. If there is, then wait squash after the next
285 * instruction (used for MIPS).
286 */
287 bool squashAfterDelaySlot[Impl::MaxThreads];
288
289
290 /** Stat for total number of idle cycles. */
291 Stats::Scalar decodeIdleCycles;
292 /** Stat for total number of blocked cycles. */
293 Stats::Scalar decodeBlockedCycles;
294 /** Stat for total number of normal running cycles. */
295 Stats::Scalar decodeRunCycles;
296 /** Stat for total number of unblocking cycles. */
297 Stats::Scalar decodeUnblockCycles;
298 /** Stat for total number of squashing cycles. */
299 Stats::Scalar decodeSquashCycles;
300 /** Stat for number of times a branch is resolved at decode. */
301 Stats::Scalar decodeBranchResolved;
302 /** Stat for number of times a branch mispredict is detected. */
303 Stats::Scalar decodeBranchMispred;
304 /** Stat for number of times decode detected a non-control instruction
305 * incorrectly predicted as a branch.
306 */
307 Stats::Scalar decodeControlMispred;
308 /** Stat for total number of decoded instructions. */
309 Stats::Scalar decodeDecodedInsts;
310 /** Stat for total number of squashed instructions. */
311 Stats::Scalar decodeSquashedInsts;
312};
313
314#endif // __CPU_O3_DECODE_HH__
| 283 /** Maximum size of the skid buffer. */
284 unsigned skidBufferMax;
285
286 /** SeqNum of Squashing Branch Delay Instruction (used for MIPS)*/
287 Addr bdelayDoneSeqNum[Impl::MaxThreads];
288
289 /** Instruction used for squashing branch (used for MIPS)*/
290 DynInstPtr squashInst[Impl::MaxThreads];
291
292 /** Tells when their is a pending delay slot inst. to send
293 * to rename. If there is, then wait squash after the next
294 * instruction (used for MIPS).
295 */
296 bool squashAfterDelaySlot[Impl::MaxThreads];
297
298
299 /** Stat for total number of idle cycles. */
300 Stats::Scalar decodeIdleCycles;
301 /** Stat for total number of blocked cycles. */
302 Stats::Scalar decodeBlockedCycles;
303 /** Stat for total number of normal running cycles. */
304 Stats::Scalar decodeRunCycles;
305 /** Stat for total number of unblocking cycles. */
306 Stats::Scalar decodeUnblockCycles;
307 /** Stat for total number of squashing cycles. */
308 Stats::Scalar decodeSquashCycles;
309 /** Stat for number of times a branch is resolved at decode. */
310 Stats::Scalar decodeBranchResolved;
311 /** Stat for number of times a branch mispredict is detected. */
312 Stats::Scalar decodeBranchMispred;
313 /** Stat for number of times decode detected a non-control instruction
314 * incorrectly predicted as a branch.
315 */
316 Stats::Scalar decodeControlMispred;
317 /** Stat for total number of decoded instructions. */
318 Stats::Scalar decodeDecodedInsts;
319 /** Stat for total number of squashed instructions. */
320 Stats::Scalar decodeSquashedInsts;
321};
322
323#endif // __CPU_O3_DECODE_HH__
|