1/*
| 1/*
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2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
| 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
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3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30
| 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30
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31#ifndef __CPU_O3_CPU_SIMPLE_DECODE_HH__ 32#define __CPU_O3_CPU_SIMPLE_DECODE_HH__
| 31#ifndef __CPU_O3_DECODE_HH__ 32#define __CPU_O3_DECODE_HH__
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33 34#include <queue> 35 36#include "base/statistics.hh" 37#include "base/timebuf.hh" 38
| 33 34#include <queue> 35 36#include "base/statistics.hh" 37#include "base/timebuf.hh" 38
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| 39/** 40 * DefaultDecode class handles both single threaded and SMT 41 * decode. Its width is specified by the parameters; each cycles it 42 * tries to decode that many instructions. Because instructions are 43 * actually decoded when the StaticInst is created, this stage does 44 * not do much other than check any PC-relative branches. 45 */
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39template<class Impl>
| 46template<class Impl>
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40class SimpleDecode
| 47class DefaultDecode
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41{ 42 private: 43 // Typedefs from the Impl. 44 typedef typename Impl::FullCPU FullCPU; 45 typedef typename Impl::DynInstPtr DynInstPtr; 46 typedef typename Impl::Params Params; 47 typedef typename Impl::CPUPol CPUPol; 48 49 // Typedefs from the CPU policy. 50 typedef typename CPUPol::FetchStruct FetchStruct; 51 typedef typename CPUPol::DecodeStruct DecodeStruct; 52 typedef typename CPUPol::TimeStruct TimeStruct; 53 54 public:
| 48{ 49 private: 50 // Typedefs from the Impl. 51 typedef typename Impl::FullCPU FullCPU; 52 typedef typename Impl::DynInstPtr DynInstPtr; 53 typedef typename Impl::Params Params; 54 typedef typename Impl::CPUPol CPUPol; 55 56 // Typedefs from the CPU policy. 57 typedef typename CPUPol::FetchStruct FetchStruct; 58 typedef typename CPUPol::DecodeStruct DecodeStruct; 59 typedef typename CPUPol::TimeStruct TimeStruct; 60 61 public:
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55 // The only time decode will become blocked is if dispatch becomes 56 // blocked, which means IQ or ROB is probably full. 57 enum Status {
| 62 /** Overall decode stage status. Used to determine if the CPU can 63 * deschedule itself due to a lack of activity. 64 */ 65 enum DecodeStatus { 66 Active, 67 Inactive 68 }; 69 70 /** Individual thread status. */ 71 enum ThreadStatus {
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58 Running, 59 Idle,
| 72 Running, 73 Idle,
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| 74 StartSquash,
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60 Squashing, 61 Blocked, 62 Unblocking 63 }; 64 65 private:
| 75 Squashing, 76 Blocked, 77 Unblocking 78 }; 79 80 private:
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66 // May eventually need statuses on a per thread basis. 67 Status _status;
| 81 /** Decode status. */ 82 DecodeStatus _status;
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68
| 83
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| 84 /** Per-thread status. */ 85 ThreadStatus decodeStatus[Impl::MaxThreads]; 86
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69 public:
| 87 public:
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70 SimpleDecode(Params ¶ms);
| 88 /** DefaultDecode constructor. */ 89 DefaultDecode(Params *params);
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71
| 90
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| 91 /** Returns the name of decode. */ 92 std::string name() const; 93 94 /** Registers statistics. */
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72 void regStats(); 73
| 95 void regStats(); 96
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| 97 /** Sets CPU pointer. */
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74 void setCPU(FullCPU *cpu_ptr); 75
| 98 void setCPU(FullCPU *cpu_ptr); 99
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| 100 /** Sets the main backwards communication time buffer pointer. */
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76 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 77
| 101 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 102
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| 103 /** Sets pointer to time buffer used to communicate to the next stage. */
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78 void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr); 79
| 104 void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr); 105
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| 106 /** Sets pointer to time buffer coming from fetch. */
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80 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 81
| 107 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 108
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| 109 /** Sets pointer to list of active threads. */ 110 void setActiveThreads(std::list<unsigned> *at_ptr); 111 112 void switchOut(); 113 114 void takeOverFrom(); 115 /** Ticks decode, processing all input signals and decoding as many 116 * instructions as possible. 117 */
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82 void tick(); 83
| 118 void tick(); 119
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84 void decode();
| 120 /** Determines what to do based on decode's current status. 121 * @param status_change decode() sets this variable if there was a status 122 * change (ie switching from from blocking to unblocking). 123 * @param tid Thread id to decode instructions from. 124 */ 125 void decode(bool &status_change, unsigned tid);
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85
| 126
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| 127 /** Processes instructions from fetch and passes them on to rename. 128 * Decoding of instructions actually happens when they are created in 129 * fetch, so this function mostly checks if PC-relative branches are 130 * correct. 131 */ 132 void decodeInsts(unsigned tid); 133
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86 private:
| 134 private:
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| 135 /** Inserts a thread's instructions into the skid buffer, to be decoded 136 * once decode unblocks. 137 */ 138 void skidInsert(unsigned tid); 139 140 /** Returns if all of the skid buffers are empty. */ 141 bool skidsEmpty(); 142 143 /** Updates overall decode status based on all of the threads' statuses. */ 144 void updateStatus(); 145 146 /** Separates instructions from fetch into individual lists of instructions 147 * sorted by thread. 148 */ 149 void sortInsts(); 150 151 /** Reads all stall signals from the backwards communication timebuffer. */ 152 void readStallSignals(unsigned tid); 153 154 /** Checks all input signals and updates decode's status appropriately. */ 155 bool checkSignalsAndUpdate(unsigned tid); 156 157 /** Checks all stall signals, and returns if any are true. */ 158 bool checkStall(unsigned tid) const; 159 160 /** Returns if there any instructions from fetch on this cycle. */
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87 inline bool fetchInstsValid(); 88
| 161 inline bool fetchInstsValid(); 162
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89 void block();
| 163 /** Switches decode to blocking, and signals back that decode has 164 * become blocked. 165 * @return Returns true if there is a status change. 166 */ 167 bool block(unsigned tid);
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90
| 168
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91 inline void unblock();
| 169 /** Switches decode to unblocking if the skid buffer is empty, and 170 * signals back that decode has unblocked. 171 * @return Returns true if there is a status change. 172 */ 173 bool unblock(unsigned tid);
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92
| 174
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93 void squash(DynInstPtr &inst);
| 175 /** Squashes if there is a PC-relative branch that was predicted 176 * incorrectly. Sends squash information back to fetch. 177 */ 178 void squash(DynInstPtr &inst, unsigned tid);
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94 95 public:
| 179 180 public:
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96 // Might want to make squash a friend function. 97 void squash();
| 181 /** Squashes due to commit signalling a squash. Changes status to 182 * squashing and clears block/unblock signals as needed. 183 */ 184 unsigned squash(unsigned tid);
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98 99 private: 100 // Interfaces to objects outside of decode. 101 /** CPU interface. */ 102 FullCPU *cpu; 103 104 /** Time buffer interface. */ 105 TimeBuffer<TimeStruct> *timeBuffer; 106 107 /** Wire to get rename's output from backwards time buffer. */ 108 typename TimeBuffer<TimeStruct>::wire fromRename; 109 110 /** Wire to get iew's information from backwards time buffer. */ 111 typename TimeBuffer<TimeStruct>::wire fromIEW; 112 113 /** Wire to get commit's information from backwards time buffer. */ 114 typename TimeBuffer<TimeStruct>::wire fromCommit; 115 116 /** Wire to write information heading to previous stages. */ 117 // Might not be the best name as not only fetch will read it. 118 typename TimeBuffer<TimeStruct>::wire toFetch; 119 120 /** Decode instruction queue. */ 121 TimeBuffer<DecodeStruct> *decodeQueue; 122 123 /** Wire used to write any information heading to rename. */ 124 typename TimeBuffer<DecodeStruct>::wire toRename; 125 126 /** Fetch instruction queue interface. */ 127 TimeBuffer<FetchStruct> *fetchQueue; 128 129 /** Wire to get fetch's output from fetch queue. */ 130 typename TimeBuffer<FetchStruct>::wire fromFetch; 131
| 185 186 private: 187 // Interfaces to objects outside of decode. 188 /** CPU interface. */ 189 FullCPU *cpu; 190 191 /** Time buffer interface. */ 192 TimeBuffer<TimeStruct> *timeBuffer; 193 194 /** Wire to get rename's output from backwards time buffer. */ 195 typename TimeBuffer<TimeStruct>::wire fromRename; 196 197 /** Wire to get iew's information from backwards time buffer. */ 198 typename TimeBuffer<TimeStruct>::wire fromIEW; 199 200 /** Wire to get commit's information from backwards time buffer. */ 201 typename TimeBuffer<TimeStruct>::wire fromCommit; 202 203 /** Wire to write information heading to previous stages. */ 204 // Might not be the best name as not only fetch will read it. 205 typename TimeBuffer<TimeStruct>::wire toFetch; 206 207 /** Decode instruction queue. */ 208 TimeBuffer<DecodeStruct> *decodeQueue; 209 210 /** Wire used to write any information heading to rename. */ 211 typename TimeBuffer<DecodeStruct>::wire toRename; 212 213 /** Fetch instruction queue interface. */ 214 TimeBuffer<FetchStruct> *fetchQueue; 215 216 /** Wire to get fetch's output from fetch queue. */ 217 typename TimeBuffer<FetchStruct>::wire fromFetch; 218
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| 219 /** Queue of all instructions coming from fetch this cycle. */ 220 std::queue<DynInstPtr> insts[Impl::MaxThreads]; 221
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132 /** Skid buffer between fetch and decode. */
| 222 /** Skid buffer between fetch and decode. */
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133 std::queue<FetchStruct> skidBuffer;
| 223 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
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134
| 224
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135 //Consider making these unsigned to avoid any confusion.
| 225 /** Variable that tracks if decode has written to the time buffer this 226 * cycle. Used to tell CPU if there is activity this cycle. 227 */ 228 bool wroteToTimeBuffer; 229 230 /** Source of possible stalls. */ 231 struct Stalls { 232 bool rename; 233 bool iew; 234 bool commit; 235 }; 236 237 /** Tracks which stages are telling decode to stall. */ 238 Stalls stalls[Impl::MaxThreads]; 239
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136 /** Rename to decode delay, in ticks. */ 137 unsigned renameToDecodeDelay; 138 139 /** IEW to decode delay, in ticks. */ 140 unsigned iewToDecodeDelay; 141 142 /** Commit to decode delay, in ticks. */ 143 unsigned commitToDecodeDelay; 144 145 /** Fetch to decode delay, in ticks. */ 146 unsigned fetchToDecodeDelay; 147 148 /** The width of decode, in instructions. */ 149 unsigned decodeWidth; 150
| 240 /** Rename to decode delay, in ticks. */ 241 unsigned renameToDecodeDelay; 242 243 /** IEW to decode delay, in ticks. */ 244 unsigned iewToDecodeDelay; 245 246 /** Commit to decode delay, in ticks. */ 247 unsigned commitToDecodeDelay; 248 249 /** Fetch to decode delay, in ticks. */ 250 unsigned fetchToDecodeDelay; 251 252 /** The width of decode, in instructions. */ 253 unsigned decodeWidth; 254
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151 /** The instruction that decode is currently on. It needs to have 152 * persistent state so that when a stall occurs in the middle of a 153 * group of instructions, it can restart at the proper instruction. 154 */ 155 unsigned numInst;
| 255 /** Index of instructions being sent to rename. */ 256 unsigned toRenameIndex;
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156
| 257
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| 258 /** number of Active Threads*/ 259 unsigned numThreads; 260 261 /** List of active thread ids */ 262 std::list<unsigned> *activeThreads; 263 264 /** Number of branches in flight. */ 265 unsigned branchCount[Impl::MaxThreads]; 266 267 /** Maximum size of the skid buffer. */ 268 unsigned skidBufferMax; 269 270 /** Stat for total number of idle cycles. */
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157 Stats::Scalar<> decodeIdleCycles;
| 271 Stats::Scalar<> decodeIdleCycles;
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| 272 /** Stat for total number of blocked cycles. */
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158 Stats::Scalar<> decodeBlockedCycles;
| 273 Stats::Scalar<> decodeBlockedCycles;
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| 274 /** Stat for total number of normal running cycles. */ 275 Stats::Scalar<> decodeRunCycles; 276 /** Stat for total number of unblocking cycles. */
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159 Stats::Scalar<> decodeUnblockCycles;
| 277 Stats::Scalar<> decodeUnblockCycles;
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| 278 /** Stat for total number of squashing cycles. */
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160 Stats::Scalar<> decodeSquashCycles;
| 279 Stats::Scalar<> decodeSquashCycles;
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| 280 /** Stat for number of times a branch is resolved at decode. */ 281 Stats::Scalar<> decodeBranchResolved; 282 /** Stat for number of times a branch mispredict is detected. */
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161 Stats::Scalar<> decodeBranchMispred;
| 283 Stats::Scalar<> decodeBranchMispred;
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| 284 /** Stat for number of times decode detected a non-control instruction 285 * incorrectly predicted as a branch. 286 */
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162 Stats::Scalar<> decodeControlMispred;
| 287 Stats::Scalar<> decodeControlMispred;
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| 288 /** Stat for total number of decoded instructions. */
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163 Stats::Scalar<> decodeDecodedInsts;
| 289 Stats::Scalar<> decodeDecodedInsts;
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| 290 /** Stat for total number of squashed instructions. */
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164 Stats::Scalar<> decodeSquashedInsts; 165}; 166
| 291 Stats::Scalar<> decodeSquashedInsts; 292}; 293
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167#endif // __CPU_O3_CPU_SIMPLE_DECODE_HH__
| 294#endif // __CPU_O3_DECODE_HH__
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