1/*
| 1/*
|
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
| 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
|
3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28
| 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28
|
29#ifndef __CPU_O3_CPU_SIMPLE_DECODE_HH__ 30#define __CPU_O3_CPU_SIMPLE_DECODE_HH__
| 29#ifndef __CPU_O3_DECODE_HH__ 30#define __CPU_O3_DECODE_HH__
|
31 32#include <queue> 33 34#include "base/statistics.hh" 35#include "base/timebuf.hh" 36
| 31 32#include <queue> 33 34#include "base/statistics.hh" 35#include "base/timebuf.hh" 36
|
| 37/** 38 * DefaultDecode class handles both single threaded and SMT 39 * decode. Its width is specified by the parameters; each cycles it 40 * tries to decode that many instructions. Because instructions are 41 * actually decoded when the StaticInst is created, this stage does 42 * not do much other than check any PC-relative branches. 43 */
|
37template<class Impl>
| 44template<class Impl>
|
38class SimpleDecode
| 45class DefaultDecode
|
39{ 40 private: 41 // Typedefs from the Impl. 42 typedef typename Impl::FullCPU FullCPU; 43 typedef typename Impl::DynInstPtr DynInstPtr; 44 typedef typename Impl::Params Params; 45 typedef typename Impl::CPUPol CPUPol; 46 47 // Typedefs from the CPU policy. 48 typedef typename CPUPol::FetchStruct FetchStruct; 49 typedef typename CPUPol::DecodeStruct DecodeStruct; 50 typedef typename CPUPol::TimeStruct TimeStruct; 51 52 public:
| 46{ 47 private: 48 // Typedefs from the Impl. 49 typedef typename Impl::FullCPU FullCPU; 50 typedef typename Impl::DynInstPtr DynInstPtr; 51 typedef typename Impl::Params Params; 52 typedef typename Impl::CPUPol CPUPol; 53 54 // Typedefs from the CPU policy. 55 typedef typename CPUPol::FetchStruct FetchStruct; 56 typedef typename CPUPol::DecodeStruct DecodeStruct; 57 typedef typename CPUPol::TimeStruct TimeStruct; 58 59 public:
|
53 // The only time decode will become blocked is if dispatch becomes 54 // blocked, which means IQ or ROB is probably full. 55 enum Status {
| 60 /** Overall decode stage status. Used to determine if the CPU can 61 * deschedule itself due to a lack of activity. 62 */ 63 enum DecodeStatus { 64 Active, 65 Inactive 66 }; 67 68 /** Individual thread status. */ 69 enum ThreadStatus {
|
56 Running, 57 Idle,
| 70 Running, 71 Idle,
|
| 72 StartSquash,
|
58 Squashing, 59 Blocked, 60 Unblocking 61 }; 62 63 private:
| 73 Squashing, 74 Blocked, 75 Unblocking 76 }; 77 78 private:
|
64 // May eventually need statuses on a per thread basis. 65 Status _status;
| 79 /** Decode status. */ 80 DecodeStatus _status;
|
66
| 81
|
| 82 /** Per-thread status. */ 83 ThreadStatus decodeStatus[Impl::MaxThreads]; 84
|
67 public:
| 85 public:
|
68 SimpleDecode(Params ¶ms);
| 86 /** DefaultDecode constructor. */ 87 DefaultDecode(Params *params);
|
69
| 88
|
| 89 /** Returns the name of decode. */ 90 std::string name() const; 91 92 /** Registers statistics. */
|
70 void regStats(); 71
| 93 void regStats(); 94
|
| 95 /** Sets CPU pointer. */
|
72 void setCPU(FullCPU *cpu_ptr); 73
| 96 void setCPU(FullCPU *cpu_ptr); 97
|
| 98 /** Sets the main backwards communication time buffer pointer. */
|
74 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 75
| 99 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 100
|
| 101 /** Sets pointer to time buffer used to communicate to the next stage. */
|
76 void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr); 77
| 102 void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr); 103
|
| 104 /** Sets pointer to time buffer coming from fetch. */
|
78 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 79
| 105 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 106
|
| 107 /** Sets pointer to list of active threads. */ 108 void setActiveThreads(std::list<unsigned> *at_ptr); 109 110 void switchOut(); 111 112 void takeOverFrom(); 113 /** Ticks decode, processing all input signals and decoding as many 114 * instructions as possible. 115 */
|
80 void tick(); 81
| 116 void tick(); 117
|
82 void decode();
| 118 /** Determines what to do based on decode's current status. 119 * @param status_change decode() sets this variable if there was a status 120 * change (ie switching from from blocking to unblocking). 121 * @param tid Thread id to decode instructions from. 122 */ 123 void decode(bool &status_change, unsigned tid);
|
83
| 124
|
| 125 /** Processes instructions from fetch and passes them on to rename. 126 * Decoding of instructions actually happens when they are created in 127 * fetch, so this function mostly checks if PC-relative branches are 128 * correct. 129 */ 130 void decodeInsts(unsigned tid); 131
|
84 private:
| 132 private:
|
| 133 /** Inserts a thread's instructions into the skid buffer, to be decoded 134 * once decode unblocks. 135 */ 136 void skidInsert(unsigned tid); 137 138 /** Returns if all of the skid buffers are empty. */ 139 bool skidsEmpty(); 140 141 /** Updates overall decode status based on all of the threads' statuses. */ 142 void updateStatus(); 143 144 /** Separates instructions from fetch into individual lists of instructions 145 * sorted by thread. 146 */ 147 void sortInsts(); 148 149 /** Reads all stall signals from the backwards communication timebuffer. */ 150 void readStallSignals(unsigned tid); 151 152 /** Checks all input signals and updates decode's status appropriately. */ 153 bool checkSignalsAndUpdate(unsigned tid); 154 155 /** Checks all stall signals, and returns if any are true. */ 156 bool checkStall(unsigned tid) const; 157 158 /** Returns if there any instructions from fetch on this cycle. */
|
85 inline bool fetchInstsValid(); 86
| 159 inline bool fetchInstsValid(); 160
|
87 void block();
| 161 /** Switches decode to blocking, and signals back that decode has 162 * become blocked. 163 * @return Returns true if there is a status change. 164 */ 165 bool block(unsigned tid);
|
88
| 166
|
89 inline void unblock();
| 167 /** Switches decode to unblocking if the skid buffer is empty, and 168 * signals back that decode has unblocked. 169 * @return Returns true if there is a status change. 170 */ 171 bool unblock(unsigned tid);
|
90
| 172
|
91 void squash(DynInstPtr &inst);
| 173 /** Squashes if there is a PC-relative branch that was predicted 174 * incorrectly. Sends squash information back to fetch. 175 */ 176 void squash(DynInstPtr &inst, unsigned tid);
|
92 93 public:
| 177 178 public:
|
94 // Might want to make squash a friend function. 95 void squash();
| 179 /** Squashes due to commit signalling a squash. Changes status to 180 * squashing and clears block/unblock signals as needed. 181 */ 182 unsigned squash(unsigned tid);
|
96 97 private: 98 // Interfaces to objects outside of decode. 99 /** CPU interface. */ 100 FullCPU *cpu; 101 102 /** Time buffer interface. */ 103 TimeBuffer<TimeStruct> *timeBuffer; 104 105 /** Wire to get rename's output from backwards time buffer. */ 106 typename TimeBuffer<TimeStruct>::wire fromRename; 107 108 /** Wire to get iew's information from backwards time buffer. */ 109 typename TimeBuffer<TimeStruct>::wire fromIEW; 110 111 /** Wire to get commit's information from backwards time buffer. */ 112 typename TimeBuffer<TimeStruct>::wire fromCommit; 113 114 /** Wire to write information heading to previous stages. */ 115 // Might not be the best name as not only fetch will read it. 116 typename TimeBuffer<TimeStruct>::wire toFetch; 117 118 /** Decode instruction queue. */ 119 TimeBuffer<DecodeStruct> *decodeQueue; 120 121 /** Wire used to write any information heading to rename. */ 122 typename TimeBuffer<DecodeStruct>::wire toRename; 123 124 /** Fetch instruction queue interface. */ 125 TimeBuffer<FetchStruct> *fetchQueue; 126 127 /** Wire to get fetch's output from fetch queue. */ 128 typename TimeBuffer<FetchStruct>::wire fromFetch; 129
| 183 184 private: 185 // Interfaces to objects outside of decode. 186 /** CPU interface. */ 187 FullCPU *cpu; 188 189 /** Time buffer interface. */ 190 TimeBuffer<TimeStruct> *timeBuffer; 191 192 /** Wire to get rename's output from backwards time buffer. */ 193 typename TimeBuffer<TimeStruct>::wire fromRename; 194 195 /** Wire to get iew's information from backwards time buffer. */ 196 typename TimeBuffer<TimeStruct>::wire fromIEW; 197 198 /** Wire to get commit's information from backwards time buffer. */ 199 typename TimeBuffer<TimeStruct>::wire fromCommit; 200 201 /** Wire to write information heading to previous stages. */ 202 // Might not be the best name as not only fetch will read it. 203 typename TimeBuffer<TimeStruct>::wire toFetch; 204 205 /** Decode instruction queue. */ 206 TimeBuffer<DecodeStruct> *decodeQueue; 207 208 /** Wire used to write any information heading to rename. */ 209 typename TimeBuffer<DecodeStruct>::wire toRename; 210 211 /** Fetch instruction queue interface. */ 212 TimeBuffer<FetchStruct> *fetchQueue; 213 214 /** Wire to get fetch's output from fetch queue. */ 215 typename TimeBuffer<FetchStruct>::wire fromFetch; 216
|
| 217 /** Queue of all instructions coming from fetch this cycle. */ 218 std::queue<DynInstPtr> insts[Impl::MaxThreads]; 219
|
130 /** Skid buffer between fetch and decode. */
| 220 /** Skid buffer between fetch and decode. */
|
131 std::queue<FetchStruct> skidBuffer;
| 221 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
|
132
| 222
|
133 //Consider making these unsigned to avoid any confusion.
| 223 /** Variable that tracks if decode has written to the time buffer this 224 * cycle. Used to tell CPU if there is activity this cycle. 225 */ 226 bool wroteToTimeBuffer; 227 228 /** Source of possible stalls. */ 229 struct Stalls { 230 bool rename; 231 bool iew; 232 bool commit; 233 }; 234 235 /** Tracks which stages are telling decode to stall. */ 236 Stalls stalls[Impl::MaxThreads]; 237
|
134 /** Rename to decode delay, in ticks. */ 135 unsigned renameToDecodeDelay; 136 137 /** IEW to decode delay, in ticks. */ 138 unsigned iewToDecodeDelay; 139 140 /** Commit to decode delay, in ticks. */ 141 unsigned commitToDecodeDelay; 142 143 /** Fetch to decode delay, in ticks. */ 144 unsigned fetchToDecodeDelay; 145 146 /** The width of decode, in instructions. */ 147 unsigned decodeWidth; 148
| 238 /** Rename to decode delay, in ticks. */ 239 unsigned renameToDecodeDelay; 240 241 /** IEW to decode delay, in ticks. */ 242 unsigned iewToDecodeDelay; 243 244 /** Commit to decode delay, in ticks. */ 245 unsigned commitToDecodeDelay; 246 247 /** Fetch to decode delay, in ticks. */ 248 unsigned fetchToDecodeDelay; 249 250 /** The width of decode, in instructions. */ 251 unsigned decodeWidth; 252
|
149 /** The instruction that decode is currently on. It needs to have 150 * persistent state so that when a stall occurs in the middle of a 151 * group of instructions, it can restart at the proper instruction. 152 */ 153 unsigned numInst;
| 253 /** Index of instructions being sent to rename. */ 254 unsigned toRenameIndex;
|
154
| 255
|
| 256 /** number of Active Threads*/ 257 unsigned numThreads; 258 259 /** List of active thread ids */ 260 std::list<unsigned> *activeThreads; 261 262 /** Number of branches in flight. */ 263 unsigned branchCount[Impl::MaxThreads]; 264 265 /** Maximum size of the skid buffer. */ 266 unsigned skidBufferMax; 267 268 /** Stat for total number of idle cycles. */
|
155 Stats::Scalar<> decodeIdleCycles;
| 269 Stats::Scalar<> decodeIdleCycles;
|
| 270 /** Stat for total number of blocked cycles. */
|
156 Stats::Scalar<> decodeBlockedCycles;
| 271 Stats::Scalar<> decodeBlockedCycles;
|
| 272 /** Stat for total number of normal running cycles. */ 273 Stats::Scalar<> decodeRunCycles; 274 /** Stat for total number of unblocking cycles. */
|
157 Stats::Scalar<> decodeUnblockCycles;
| 275 Stats::Scalar<> decodeUnblockCycles;
|
| 276 /** Stat for total number of squashing cycles. */
|
158 Stats::Scalar<> decodeSquashCycles;
| 277 Stats::Scalar<> decodeSquashCycles;
|
| 278 /** Stat for number of times a branch is resolved at decode. */ 279 Stats::Scalar<> decodeBranchResolved; 280 /** Stat for number of times a branch mispredict is detected. */
|
159 Stats::Scalar<> decodeBranchMispred;
| 281 Stats::Scalar<> decodeBranchMispred;
|
| 282 /** Stat for number of times decode detected a non-control instruction 283 * incorrectly predicted as a branch. 284 */
|
160 Stats::Scalar<> decodeControlMispred;
| 285 Stats::Scalar<> decodeControlMispred;
|
| 286 /** Stat for total number of decoded instructions. */
|
161 Stats::Scalar<> decodeDecodedInsts;
| 287 Stats::Scalar<> decodeDecodedInsts;
|
| 288 /** Stat for total number of squashed instructions. */
|
162 Stats::Scalar<> decodeSquashedInsts; 163}; 164
| 289 Stats::Scalar<> decodeSquashedInsts; 290}; 291
|
165#endif // __CPU_O3_CPU_SIMPLE_DECODE_HH__
| 292#endif // __CPU_O3_DECODE_HH__
|
| |