cpu.hh (9523:b8c8437f71d9) cpu.hh (9608:e2b6b86fda03)
1/*
1/*
2 * Copyright (c) 2011-2012 ARM Limited
2 * Copyright (c) 2011-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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124 /** Overall CPU status. */
125 Status _status;
126
127 private:
128
129 /**
130 * IcachePort class for instruction fetch.
131 */
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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124 /** Overall CPU status. */
125 Status _status;
126
127 private:
128
129 /**
130 * IcachePort class for instruction fetch.
131 */
132 class IcachePort : public CpuPort
132 class IcachePort : public MasterPort
133 {
134 protected:
135 /** Pointer to fetch. */
136 DefaultFetch<Impl> *fetch;
137
138 public:
139 /** Default constructor. */
140 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
133 {
134 protected:
135 /** Pointer to fetch. */
136 DefaultFetch<Impl> *fetch;
137
138 public:
139 /** Default constructor. */
140 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
141 : CpuPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
141 : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
142 { }
143
144 protected:
145
146 /** Timing version of receive. Handles setting fetch to the
147 * proper status to start fetching. */
148 virtual bool recvTimingResp(PacketPtr pkt);
149 virtual void recvTimingSnoopReq(PacketPtr pkt) { }
150
151 /** Handles doing a retry of a failed fetch. */
152 virtual void recvRetry();
153 };
154
155 /**
156 * DcachePort class for the load/store queue.
157 */
142 { }
143
144 protected:
145
146 /** Timing version of receive. Handles setting fetch to the
147 * proper status to start fetching. */
148 virtual bool recvTimingResp(PacketPtr pkt);
149 virtual void recvTimingSnoopReq(PacketPtr pkt) { }
150
151 /** Handles doing a retry of a failed fetch. */
152 virtual void recvRetry();
153 };
154
155 /**
156 * DcachePort class for the load/store queue.
157 */
158 class DcachePort : public CpuPort
158 class DcachePort : public MasterPort
159 {
160 protected:
161
162 /** Pointer to LSQ. */
163 LSQ<Impl> *lsq;
164
165 public:
166 /** Default constructor. */
167 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
159 {
160 protected:
161
162 /** Pointer to LSQ. */
163 LSQ<Impl> *lsq;
164
165 public:
166 /** Default constructor. */
167 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
168 : CpuPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq)
168 : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq)
169 { }
170
171 protected:
172
173 /** Timing version of receive. Handles writing back and
174 * completing the load or store that has returned from
175 * memory. */
176 virtual bool recvTimingResp(PacketPtr pkt);
177 virtual void recvTimingSnoopReq(PacketPtr pkt);
178
169 { }
170
171 protected:
172
173 /** Timing version of receive. Handles writing back and
174 * completing the load or store that has returned from
175 * memory. */
176 virtual bool recvTimingResp(PacketPtr pkt);
177 virtual void recvTimingSnoopReq(PacketPtr pkt);
178
179 virtual void recvFunctionalSnoop(PacketPtr pkt)
180 {
181 // @todo: Is there a need for potential invalidation here?
182 }
183
179 /** Handles doing a retry of the previous send. */
180 virtual void recvRetry();
181
182 /**
183 * As this CPU requires snooping to maintain the load store queue
184 * change the behaviour from the base CPU port.
185 *
186 * @return true since we have to snoop

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802 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
803 uint8_t *data, int store_idx)
804 {
805 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
806 data, store_idx);
807 }
808
809 /** Used by the fetch unit to get a hold of the instruction port. */
184 /** Handles doing a retry of the previous send. */
185 virtual void recvRetry();
186
187 /**
188 * As this CPU requires snooping to maintain the load store queue
189 * change the behaviour from the base CPU port.
190 *
191 * @return true since we have to snoop

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807 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
808 uint8_t *data, int store_idx)
809 {
810 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
811 data, store_idx);
812 }
813
814 /** Used by the fetch unit to get a hold of the instruction port. */
810 virtual CpuPort &getInstPort() { return icachePort; }
815 virtual MasterPort &getInstPort() { return icachePort; }
811
812 /** Get the dcache port (used to find block size for translations). */
816
817 /** Get the dcache port (used to find block size for translations). */
813 virtual CpuPort &getDataPort() { return dcachePort; }
818 virtual MasterPort &getDataPort() { return dcachePort; }
814
815 /** Stat for total number of times the CPU is descheduled. */
816 Stats::Scalar timesIdled;
817 /** Stat for total number of cycles the CPU spends descheduled. */
818 Stats::Scalar idleCycles;
819 /** Stat for total number of cycles the CPU spends descheduled due to a
820 * quiesce operation or waiting for an interrupt. */
821 Stats::Scalar quiesceCycles;

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820 /** Stat for total number of times the CPU is descheduled. */
821 Stats::Scalar timesIdled;
822 /** Stat for total number of cycles the CPU spends descheduled. */
823 Stats::Scalar idleCycles;
824 /** Stat for total number of cycles the CPU spends descheduled due to a
825 * quiesce operation or waiting for an interrupt. */
826 Stats::Scalar quiesceCycles;

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