| cpu.hh (9342:6fec8f26e56d) | cpu.hh (9384:877293183bdf) |
|---|---|
| 1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 620 unchanged lines hidden (view full) --- 629 typename CPUPolicy::ROB rob; 630 631 /** Active Threads List */ 632 std::list<ThreadID> activeThreads; 633 634 /** Integer Register Scoreboard */ 635 Scoreboard scoreboard; 636 | 1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 620 unchanged lines hidden (view full) --- 629 typename CPUPolicy::ROB rob; 630 631 /** Active Threads List */ 632 std::list<ThreadID> activeThreads; 633 634 /** Integer Register Scoreboard */ 635 Scoreboard scoreboard; 636 |
| 637 TheISA::ISA isa[Impl::MaxThreads]; | 637 std::vector<TheISA::ISA *> isa; |
| 638 639 /** Instruction port. Note that it has to appear after the fetch stage. */ 640 IcachePort icachePort; 641 642 /** Data port. Note that it has to appear after the iew stages */ 643 DcachePort dcachePort; 644 645 public: --- 178 unchanged lines hidden --- | 638 639 /** Instruction port. Note that it has to appear after the fetch stage. */ 640 IcachePort icachePort; 641 642 /** Data port. Note that it has to appear after the iew stages */ 643 DcachePort dcachePort; 644 645 public: --- 178 unchanged lines hidden --- |