cpu.hh (8975:7f36d4436074) | cpu.hh (9095:0e6bd7082fac) |
---|---|
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 127 unchanged lines hidden (view full) --- 136 { 137 protected: 138 /** Pointer to fetch. */ 139 DefaultFetch<Impl> *fetch; 140 141 public: 142 /** Default constructor. */ 143 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu) | 1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 127 unchanged lines hidden (view full) --- 136 { 137 protected: 138 /** Pointer to fetch. */ 139 DefaultFetch<Impl> *fetch; 140 141 public: 142 /** Default constructor. */ 143 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu) |
144 : CpuPort(_fetch->name() + "-iport", _cpu), fetch(_fetch) | 144 : CpuPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch) |
145 { } 146 147 protected: 148 149 /** Timing version of receive. Handles setting fetch to the 150 * proper status to start fetching. */ 151 virtual bool recvTimingResp(PacketPtr pkt); 152 virtual void recvTimingSnoopReq(PacketPtr pkt) { } --- 10 unchanged lines hidden (view full) --- 163 protected: 164 165 /** Pointer to LSQ. */ 166 LSQ<Impl> *lsq; 167 168 public: 169 /** Default constructor. */ 170 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu) | 145 { } 146 147 protected: 148 149 /** Timing version of receive. Handles setting fetch to the 150 * proper status to start fetching. */ 151 virtual bool recvTimingResp(PacketPtr pkt); 152 virtual void recvTimingSnoopReq(PacketPtr pkt) { } --- 10 unchanged lines hidden (view full) --- 163 protected: 164 165 /** Pointer to LSQ. */ 166 LSQ<Impl> *lsq; 167 168 public: 169 /** Default constructor. */ 170 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu) |
171 : CpuPort(_lsq->name() + "-dport", _cpu), lsq(_lsq) | 171 : CpuPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq) |
172 { } 173 174 protected: 175 176 /** Timing version of receive. Handles writing back and 177 * completing the load or store that has returned from 178 * memory. */ 179 virtual bool recvTimingResp(PacketPtr pkt); --- 643 unchanged lines hidden --- | 172 { } 173 174 protected: 175 176 /** Timing version of receive. Handles writing back and 177 * completing the load or store that has returned from 178 * memory. */ 179 virtual bool recvTimingResp(PacketPtr pkt); --- 643 unchanged lines hidden --- |