cpu.hh (8948:e95ee70f876c) cpu.hh (8975:7f36d4436074)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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143 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
144 : CpuPort(_fetch->name() + "-iport", _cpu), fetch(_fetch)
145 { }
146
147 protected:
148
149 /** Timing version of receive. Handles setting fetch to the
150 * proper status to start fetching. */
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 134 unchanged lines hidden (view full) ---

143 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
144 : CpuPort(_fetch->name() + "-iport", _cpu), fetch(_fetch)
145 { }
146
147 protected:
148
149 /** Timing version of receive. Handles setting fetch to the
150 * proper status to start fetching. */
151 virtual bool recvTiming(PacketPtr pkt);
152 virtual bool recvTimingSnoop(PacketPtr pkt) { return true; }
151 virtual bool recvTimingResp(PacketPtr pkt);
152 virtual void recvTimingSnoopReq(PacketPtr pkt) { }
153
154 /** Handles doing a retry of a failed fetch. */
155 virtual void recvRetry();
156 };
157
158 /**
159 * DcachePort class for the load/store queue.
160 */

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171 : CpuPort(_lsq->name() + "-dport", _cpu), lsq(_lsq)
172 { }
173
174 protected:
175
176 /** Timing version of receive. Handles writing back and
177 * completing the load or store that has returned from
178 * memory. */
153
154 /** Handles doing a retry of a failed fetch. */
155 virtual void recvRetry();
156 };
157
158 /**
159 * DcachePort class for the load/store queue.
160 */

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171 : CpuPort(_lsq->name() + "-dport", _cpu), lsq(_lsq)
172 { }
173
174 protected:
175
176 /** Timing version of receive. Handles writing back and
177 * completing the load or store that has returned from
178 * memory. */
179 virtual bool recvTiming(PacketPtr pkt);
180 virtual bool recvTimingSnoop(PacketPtr pkt);
179 virtual bool recvTimingResp(PacketPtr pkt);
180 virtual void recvTimingSnoopReq(PacketPtr pkt);
181
182 /** Handles doing a retry of the previous send. */
183 virtual void recvRetry();
184
185 /**
186 * As this CPU requires snooping to maintain the load store queue
187 * change the behaviour from the base CPU port.
188 *

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182 /** Handles doing a retry of the previous send. */
183 virtual void recvRetry();
184
185 /**
186 * As this CPU requires snooping to maintain the load store queue
187 * change the behaviour from the base CPU port.
188 *

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