cpu.hh (8922:17f037ad8918) | cpu.hh (8948:e95ee70f876c) |
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1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 135 unchanged lines hidden (view full) --- 144 : CpuPort(_fetch->name() + "-iport", _cpu), fetch(_fetch) 145 { } 146 147 protected: 148 149 /** Timing version of receive. Handles setting fetch to the 150 * proper status to start fetching. */ 151 virtual bool recvTiming(PacketPtr pkt); | 1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 135 unchanged lines hidden (view full) --- 144 : CpuPort(_fetch->name() + "-iport", _cpu), fetch(_fetch) 145 { } 146 147 protected: 148 149 /** Timing version of receive. Handles setting fetch to the 150 * proper status to start fetching. */ 151 virtual bool recvTiming(PacketPtr pkt); |
152 virtual bool recvTimingSnoop(PacketPtr pkt) { return true; } |
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152 153 /** Handles doing a retry of a failed fetch. */ 154 virtual void recvRetry(); 155 }; 156 157 /** 158 * DcachePort class for the load/store queue. 159 */ --- 11 unchanged lines hidden (view full) --- 171 { } 172 173 protected: 174 175 /** Timing version of receive. Handles writing back and 176 * completing the load or store that has returned from 177 * memory. */ 178 virtual bool recvTiming(PacketPtr pkt); | 153 154 /** Handles doing a retry of a failed fetch. */ 155 virtual void recvRetry(); 156 }; 157 158 /** 159 * DcachePort class for the load/store queue. 160 */ --- 11 unchanged lines hidden (view full) --- 172 { } 173 174 protected: 175 176 /** Timing version of receive. Handles writing back and 177 * completing the load or store that has returned from 178 * memory. */ 179 virtual bool recvTiming(PacketPtr pkt); |
180 virtual bool recvTimingSnoop(PacketPtr pkt); |
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179 180 /** Handles doing a retry of the previous send. */ 181 virtual void recvRetry(); 182 183 /** 184 * As this CPU requires snooping to maintain the load store queue 185 * change the behaviour from the base CPU port. 186 * --- 634 unchanged lines hidden --- | 181 182 /** Handles doing a retry of the previous send. */ 183 virtual void recvRetry(); 184 185 /** 186 * As this CPU requires snooping to maintain the load store queue 187 * change the behaviour from the base CPU port. 188 * --- 634 unchanged lines hidden --- |