cpu.hh (8834:21e8d54ecf07) cpu.hh (8850:ed91b534ed04)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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356 this->itb->demapPage(vaddr, asn);
357 }
358
359 void demapDataPage(Addr vaddr, uint64_t asn)
360 {
361 this->dtb->demapPage(vaddr, asn);
362 }
363
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 347 unchanged lines hidden (view full) ---

356 this->itb->demapPage(vaddr, asn);
357 }
358
359 void demapDataPage(Addr vaddr, uint64_t asn)
360 {
361 this->dtb->demapPage(vaddr, asn);
362 }
363
364 /** Returns a specific port. */
365 Port *getPort(const std::string &if_name, int idx);
366
367 /** Ticks CPU, calling tick() on each stage, and checking the overall
368 * activity to see if the CPU should deschedule itself.
369 */
370 void tick();
371
372 /** Initialize the CPU */
373 void init();
374

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776 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
777 uint8_t *data, int store_idx)
778 {
779 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
780 data, store_idx);
781 }
782
783 /** Used by the fetch unit to get a hold of the instruction port. */
364 /** Ticks CPU, calling tick() on each stage, and checking the overall
365 * activity to see if the CPU should deschedule itself.
366 */
367 void tick();
368
369 /** Initialize the CPU */
370 void init();
371

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773 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
774 uint8_t *data, int store_idx)
775 {
776 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
777 data, store_idx);
778 }
779
780 /** Used by the fetch unit to get a hold of the instruction port. */
784 Port* getIcachePort() { return &icachePort; }
781 virtual CpuPort &getInstPort() { return icachePort; }
785
786 /** Get the dcache port (used to find block size for translations). */
782
783 /** Get the dcache port (used to find block size for translations). */
787 Port* getDcachePort() { return &dcachePort; }
784 virtual CpuPort &getDataPort() { return dcachePort; }
788
789 Addr lockAddr;
790
791 /** Temporary fix for the lock flag, works in the UP case. */
792 bool lockFlag;
793
794 /** Stat for total number of times the CPU is descheduled. */
795 Stats::Scalar timesIdled;

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786 Addr lockAddr;
787
788 /** Temporary fix for the lock flag, works in the UP case. */
789 bool lockFlag;
790
791 /** Stat for total number of times the CPU is descheduled. */
792 Stats::Scalar timesIdled;

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