cpu.hh (8737:770ccf3af571) cpu.hh (8777:dd43f1c9fa0a)
1/*
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;

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74class ThreadContext;
75template <class>
76class O3ThreadContext;
77
78class Checkpoint;
79class MemObject;
80class Process;
81
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * Copyright (c) 2011 Regents of the University of California
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;

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62class ThreadContext;
63template <class>
64class O3ThreadContext;
65
66class Checkpoint;
67class MemObject;
68class Process;
69
82struct BaseCPUParams;
70class BaseCPUParams;
83
84class BaseO3CPU : public BaseCPU
85{
86 //Stuff that's pretty ISA independent will go here.
87 public:
88 BaseO3CPU(BaseCPUParams *params);
89
90 void regStats();

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125
126 /** Overall CPU status. */
127 Status _status;
128
129 /** Per-thread status in CPU, used for SMT. */
130 Status _threadStatus[Impl::MaxThreads];
131
132 private:
71
72class BaseO3CPU : public BaseCPU
73{
74 //Stuff that's pretty ISA independent will go here.
75 public:
76 BaseO3CPU(BaseCPUParams *params);
77
78 void regStats();

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113
114 /** Overall CPU status. */
115 Status _status;
116
117 /** Per-thread status in CPU, used for SMT. */
118 Status _threadStatus[Impl::MaxThreads];
119
120 private:
133
134 /**
135 * IcachePort class for instruction fetch.
136 */
137 class IcachePort : public CpuPort
138 {
139 protected:
140 /** Pointer to fetch. */
141 DefaultFetch<Impl> *fetch;
142
143 public:
144 /** Default constructor. */
145 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
146 : CpuPort(_fetch->name() + "-iport", _cpu), fetch(_fetch)
147 { }
148
149 protected:
150
151 /** Timing version of receive. Handles setting fetch to the
152 * proper status to start fetching. */
153 virtual bool recvTiming(PacketPtr pkt);
154
155 /** Handles doing a retry of a failed fetch. */
156 virtual void recvRetry();
157 };
158
159 /**
160 * DcachePort class for the load/store queue.
161 */
162 class DcachePort : public CpuPort
163 {
164 protected:
165
166 /** Pointer to LSQ. */
167 LSQ<Impl> *lsq;
168
169 public:
170 /** Default constructor. */
171 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
172 : CpuPort(_lsq->name() + "-dport", _cpu), lsq(_lsq)
173 { }
174
175 protected:
176
177 /** Timing version of receive. Handles writing back and
178 * completing the load or store that has returned from
179 * memory. */
180 virtual bool recvTiming(PacketPtr pkt);
181
182 /** Handles doing a retry of the previous send. */
183 virtual void recvRetry();
184
185 /**
186 * As this CPU requires snooping to maintain the load store queue
187 * change the behaviour from the base CPU port.
188 *
189 * @return true since we have to snoop
190 */
191 virtual bool isSnooping()
192 { return true; }
193 };
194
195 class TickEvent : public Event
196 {
197 private:
198 /** Pointer to the CPU. */
199 FullO3CPU<Impl> *cpu;
200
201 public:
202 /** Constructs a tick event. */

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396 void activateContext(ThreadID tid, int delay);
397
398 /** Remove Thread from Active Threads List */
399 void suspendContext(ThreadID tid);
400
401 /** Remove Thread from Active Threads List &&
402 * Possibly Remove Thread Context from CPU.
403 */
121 class TickEvent : public Event
122 {
123 private:
124 /** Pointer to the CPU. */
125 FullO3CPU<Impl> *cpu;
126
127 public:
128 /** Constructs a tick event. */

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322 void activateContext(ThreadID tid, int delay);
323
324 /** Remove Thread from Active Threads List */
325 void suspendContext(ThreadID tid);
326
327 /** Remove Thread from Active Threads List &&
328 * Possibly Remove Thread Context from CPU.
329 */
404 bool scheduleDeallocateContext(ThreadID tid, bool remove, int delay = 1);
330 bool deallocateContext(ThreadID tid, bool remove, int delay = 1);
405
406 /** Remove Thread from Active Threads List &&
407 * Remove Thread Context from CPU.
408 */
409 void haltContext(ThreadID tid);
410
411 /** Activate a Thread When CPU Resources are Available. */
412 void activateWhenReady(ThreadID tid);

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419
420 /** Serialize state. */
421 virtual void serialize(std::ostream &os);
422
423 /** Unserialize from a checkpoint. */
424 virtual void unserialize(Checkpoint *cp, const std::string &section);
425
426 public:
331
332 /** Remove Thread from Active Threads List &&
333 * Remove Thread Context from CPU.
334 */
335 void haltContext(ThreadID tid);
336
337 /** Activate a Thread When CPU Resources are Available. */
338 void activateWhenReady(ThreadID tid);

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345
346 /** Serialize state. */
347 virtual void serialize(std::ostream &os);
348
349 /** Unserialize from a checkpoint. */
350 virtual void unserialize(Checkpoint *cp, const std::string &section);
351
352 public:
427#if !FULL_SYSTEM
428 /** Executes a syscall.
429 * @todo: Determine if this needs to be virtual.
430 */
431 void syscall(int64_t callnum, ThreadID tid);
353 /** Executes a syscall.
354 * @todo: Determine if this needs to be virtual.
355 */
356 void syscall(int64_t callnum, ThreadID tid);
432#endif
433
434 /** Starts draining the CPU's pipeline of all instructions in
435 * order to stop all memory accesses. */
436 virtual unsigned int drain(Event *drain_event);
437
438 /** Resumes execution after a drain. */
439 virtual void resume();
440

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464 Fault getInterrupts();
465
466 /** Processes any an interrupt fault. */
467 void processInterrupts(Fault interrupt);
468
469 /** Halts the CPU. */
470 void halt() { panic("Halt not implemented!\n"); }
471
357
358 /** Starts draining the CPU's pipeline of all instructions in
359 * order to stop all memory accesses. */
360 virtual unsigned int drain(Event *drain_event);
361
362 /** Resumes execution after a drain. */
363 virtual void resume();
364

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388 Fault getInterrupts();
389
390 /** Processes any an interrupt fault. */
391 void processInterrupts(Fault interrupt);
392
393 /** Halts the CPU. */
394 void halt() { panic("Halt not implemented!\n"); }
395
396 /** Update the Virt and Phys ports of all ThreadContexts to
397 * reflect change in memory connections. */
398 void updateMemPorts();
399
472 /** Check if this address is a valid instruction address. */
473 bool validInstAddr(Addr addr) { return true; }
474
475 /** Check if this address is a valid data address. */
476 bool validDataAddr(Addr addr) { return true; }
477#endif
478
479 /** Register accessors. Index refers to the physical register index. */

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635 /** Active Threads List */
636 std::list<ThreadID> activeThreads;
637
638 /** Integer Register Scoreboard */
639 Scoreboard scoreboard;
640
641 TheISA::ISA isa[Impl::MaxThreads];
642
400 /** Check if this address is a valid instruction address. */
401 bool validInstAddr(Addr addr) { return true; }
402
403 /** Check if this address is a valid data address. */
404 bool validDataAddr(Addr addr) { return true; }
405#endif
406
407 /** Register accessors. Index refers to the physical register index. */

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563 /** Active Threads List */
564 std::list<ThreadID> activeThreads;
565
566 /** Integer Register Scoreboard */
567 Scoreboard scoreboard;
568
569 TheISA::ISA isa[Impl::MaxThreads];
570
643 /** Instruction port. Note that it has to appear after the fetch stage. */
644 IcachePort icachePort;
645
646 /** Data port. Note that it has to appear after the iew stages */
647 DcachePort dcachePort;
648
649 public:
650 /** Enum to give each stage a specific index, so when calling
651 * activateStage() or deactivateStage(), they can specify which stage
652 * is being activated/deactivated.
653 */
654 enum StageIdx {
655 FetchIdx,
656 DecodeIdx,

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727 /** The global sequence number counter. */
728 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
729
730#if USE_CHECKER
731 /** Pointer to the checker, which can dynamically verify
732 * instruction results at run time. This can be set to NULL if it
733 * is not being used.
734 */
571 public:
572 /** Enum to give each stage a specific index, so when calling
573 * activateStage() or deactivateStage(), they can specify which stage
574 * is being activated/deactivated.
575 */
576 enum StageIdx {
577 FetchIdx,
578 DecodeIdx,

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649 /** The global sequence number counter. */
650 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
651
652#if USE_CHECKER
653 /** Pointer to the checker, which can dynamically verify
654 * instruction results at run time. This can be set to NULL if it
655 * is not being used.
656 */
735 Checker<Impl> *checker;
657 Checker<DynInstPtr> *checker;
736#endif
737
738 /** Pointer to the system. */
739 System *system;
740
741 /** Event to call process() on once draining has completed. */
742 Event *drainEvent;
743

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779 /** CPU write function, forwards write to LSQ. */
780 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
781 uint8_t *data, int store_idx)
782 {
783 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
784 data, store_idx);
785 }
786
658#endif
659
660 /** Pointer to the system. */
661 System *system;
662
663 /** Event to call process() on once draining has completed. */
664 Event *drainEvent;
665

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701 /** CPU write function, forwards write to LSQ. */
702 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
703 uint8_t *data, int store_idx)
704 {
705 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
706 data, store_idx);
707 }
708
787 /** Used by the fetch unit to get a hold of the instruction port. */
788 Port* getIcachePort() { return &icachePort; }
789
790 /** Get the dcache port (used to find block size for translations). */
709 /** Get the dcache port (used to find block size for translations). */
791 Port* getDcachePort() { return &dcachePort; }
710 Port *getDcachePort() { return this->iew.ldstQueue.getDcachePort(); }
792
793 Addr lockAddr;
794
795 /** Temporary fix for the lock flag, works in the UP case. */
796 bool lockFlag;
797
798 /** Stat for total number of times the CPU is descheduled. */
799 Stats::Scalar timesIdled;
800 /** Stat for total number of cycles the CPU spends descheduled. */
801 Stats::Scalar idleCycles;
711
712 Addr lockAddr;
713
714 /** Temporary fix for the lock flag, works in the UP case. */
715 bool lockFlag;
716
717 /** Stat for total number of times the CPU is descheduled. */
718 Stats::Scalar timesIdled;
719 /** Stat for total number of cycles the CPU spends descheduled. */
720 Stats::Scalar idleCycles;
802 /** Stat for total number of cycles the CPU spends descheduled due to a
803 * quiesce operation or waiting for an interrupt. */
804 Stats::Scalar quiesceCycles;
805 /** Stat for the number of committed instructions per thread. */
806 Stats::Vector committedInsts;
807 /** Stat for the total number of committed instructions. */
808 Stats::Scalar totalCommittedInsts;
809 /** Stat for the CPI per thread. */
810 Stats::Formula cpi;
811 /** Stat for the total CPI. */
812 Stats::Formula totalCpi;

--- 17 unchanged lines hidden --- 		721 /** Stat for the number of committed instructions per thread. */
722 Stats::Vector committedInsts;
723 /** Stat for the total number of committed instructions. */
724 Stats::Scalar totalCommittedInsts;
725 /** Stat for the CPI per thread. */
726 Stats::Formula cpi;
727 /** Stat for the total CPI. */
728 Stats::Formula totalCpi;

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