cpu.hh (8706:b1838faf3bcc) cpu.hh (8707:489489c67fd9)
1/*
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * Copyright (c) 2011 Regents of the University of California
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;

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113
114 /** Overall CPU status. */
115 Status _status;
116
117 /** Per-thread status in CPU, used for SMT. */
118 Status _threadStatus[Impl::MaxThreads];
119
120 private:
14 * Copyright (c) 2004-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;

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125
126 /** Overall CPU status. */
127 Status _status;
128
129 /** Per-thread status in CPU, used for SMT. */
130 Status _threadStatus[Impl::MaxThreads];
131
132 private:
133
134 /**
135 * IcachePort class for instruction fetch.
136 */
137 class IcachePort : public CpuPort
138 {
139 protected:
140 /** Pointer to fetch. */
141 DefaultFetch<Impl> *fetch;
142
143 public:
144 /** Default constructor. */
145 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
146 : CpuPort(_fetch->name() + "-iport", _cpu), fetch(_fetch)
147 { }
148
149 protected:
150
151 /** Timing version of receive. Handles setting fetch to the
152 * proper status to start fetching. */
153 virtual bool recvTiming(PacketPtr pkt);
154
155 /** Handles doing a retry of a failed fetch. */
156 virtual void recvRetry();
157 };
158
159 /**
160 * DcachePort class for the load/store queue.
161 */
162 class DcachePort : public CpuPort
163 {
164 protected:
165
166 /** Pointer to LSQ. */
167 LSQ<Impl> *lsq;
168
169 public:
170 /** Default constructor. */
171 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
172 : CpuPort(_lsq->name() + "-dport", _cpu), lsq(_lsq)
173 { }
174
175 protected:
176
177 /** Timing version of receive. Handles writing back and
178 * completing the load or store that has returned from
179 * memory. */
180 virtual bool recvTiming(PacketPtr pkt);
181
182 /** Handles doing a retry of the previous send. */
183 virtual void recvRetry();
184
185 /**
186 * As this CPU requires snooping to maintain the load store queue
187 * change the behaviour from the base CPU port.
188 *
189 * @param resp list of ranges this port responds to
190 * @param snoop indicating if the port snoops or not
191 */
192 virtual void getDeviceAddressRanges(AddrRangeList& resp,
193 bool& snoop)
194 { resp.clear(); snoop = true; }
195 };
196
121 class TickEvent : public Event
122 {
123 private:
124 /** Pointer to the CPU. */
125 FullO3CPU<Impl> *cpu;
126
127 public:
128 /** Constructs a tick event. */

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561 /** Active Threads List */
562 std::list<ThreadID> activeThreads;
563
564 /** Integer Register Scoreboard */
565 Scoreboard scoreboard;
566
567 TheISA::ISA isa[Impl::MaxThreads];
568
197 class TickEvent : public Event
198 {
199 private:
200 /** Pointer to the CPU. */
201 FullO3CPU<Impl> *cpu;
202
203 public:
204 /** Constructs a tick event. */

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637 /** Active Threads List */
638 std::list<ThreadID> activeThreads;
639
640 /** Integer Register Scoreboard */
641 Scoreboard scoreboard;
642
643 TheISA::ISA isa[Impl::MaxThreads];
644
645 /** Instruction port. Note that it has to appear after the fetch stage. */
646 IcachePort icachePort;
647
648 /** Data port. Note that it has to appear after the iew stages */
649 DcachePort dcachePort;
650
569 public:
570 /** Enum to give each stage a specific index, so when calling
571 * activateStage() or deactivateStage(), they can specify which stage
572 * is being activated/deactivated.
573 */
574 enum StageIdx {
575 FetchIdx,
576 DecodeIdx,

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699 /** CPU write function, forwards write to LSQ. */
700 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
701 uint8_t *data, int store_idx)
702 {
703 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
704 data, store_idx);
705 }
706
651 public:
652 /** Enum to give each stage a specific index, so when calling
653 * activateStage() or deactivateStage(), they can specify which stage
654 * is being activated/deactivated.
655 */
656 enum StageIdx {
657 FetchIdx,
658 DecodeIdx,

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781 /** CPU write function, forwards write to LSQ. */
782 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
783 uint8_t *data, int store_idx)
784 {
785 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
786 data, store_idx);
787 }
788
789 /** Used by the fetch unit to get a hold of the instruction port. */
790 Port* getIcachePort() { return &icachePort; }
791
707 /** Get the dcache port (used to find block size for translations). */
792 /** Get the dcache port (used to find block size for translations). */
708 Port *getDcachePort() { return this->iew.ldstQueue.getDcachePort(); }
793 Port* getDcachePort() { return &dcachePort; }
709
710 Addr lockAddr;
711
712 /** Temporary fix for the lock flag, works in the UP case. */
713 bool lockFlag;
714
715 /** Stat for total number of times the CPU is descheduled. */
716 Stats::Scalar timesIdled;

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795 Addr lockAddr;
796
797 /** Temporary fix for the lock flag, works in the UP case. */
798 bool lockFlag;
799
800 /** Stat for total number of times the CPU is descheduled. */
801 Stats::Scalar timesIdled;

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