cpu.hh (6711:c79d72abdbe5) cpu.hh (6974:4d4903a3e7c5)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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698 /** Mapping for system thread id to cpu id */
699 std::map<ThreadID, unsigned> threadMap;
700
701 /** Available thread ids in the cpu*/
702 std::vector<ThreadID> tids;
703
704 /** CPU read function, forwards read to LSQ. */
705 template <class T>
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 689 unchanged lines hidden (view full) ---

698 /** Mapping for system thread id to cpu id */
699 std::map<ThreadID, unsigned> threadMap;
700
701 /** Available thread ids in the cpu*/
702 std::vector<ThreadID> tids;
703
704 /** CPU read function, forwards read to LSQ. */
705 template <class T>
706 Fault read(RequestPtr &req, T &data, int load_idx)
706 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
707 T &data, int load_idx)
707 {
708 {
708 return this->iew.ldstQueue.read(req, data, load_idx);
709 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh,
710 data, load_idx);
709 }
710
711 /** CPU write function, forwards write to LSQ. */
712 template <class T>
711 }
712
713 /** CPU write function, forwards write to LSQ. */
714 template <class T>
713 Fault write(RequestPtr &req, T &data, int store_idx)
715 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
716 T &data, int store_idx)
714 {
717 {
715 return this->iew.ldstQueue.write(req, data, store_idx);
718 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
719 data, store_idx);
716 }
717
720 }
721
722 /** Get the dcache port (used to find block size for translations). */
723 Port *getDcachePort() { return this->iew.ldstQueue.getDcachePort(); }
724
718 Addr lockAddr;
719
720 /** Temporary fix for the lock flag, works in the UP case. */
721 bool lockFlag;
722
723 /** Stat for total number of times the CPU is descheduled. */
724 Stats::Scalar timesIdled;
725 /** Stat for total number of cycles the CPU spends descheduled. */

--- 16 unchanged lines hidden --- 		725 Addr lockAddr;
726
727 /** Temporary fix for the lock flag, works in the UP case. */
728 bool lockFlag;
729
730 /** Stat for total number of times the CPU is descheduled. */
731 Stats::Scalar timesIdled;
732 /** Stat for total number of cycles the CPU spends descheduled. */

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