cpu.hh (5529:9ae69b9cd7fd) cpu.hh (5595:6ebdae3f619b)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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94class FullO3CPU : public BaseO3CPU
95{
96 public:
97 // Typedefs from the Impl here.
98 typedef typename Impl::CPUPol CPUPolicy;
99 typedef typename Impl::DynInstPtr DynInstPtr;
100 typedef typename Impl::O3CPU O3CPU;
101
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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94class FullO3CPU : public BaseO3CPU
95{
96 public:
97 // Typedefs from the Impl here.
98 typedef typename Impl::CPUPol CPUPolicy;
99 typedef typename Impl::DynInstPtr DynInstPtr;
100 typedef typename Impl::O3CPU O3CPU;
101
102 typedef O3ThreadState<Impl> ImplState;
102 typedef O3ThreadState<Impl> Thread;
103
104 typedef typename std::list<DynInstPtr>::iterator ListIt;
105
106 friend class O3ThreadContext<Impl>;
107
108 public:
109 enum Status {

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196
197 /** Unschedule actiavte thread event, regardless of its current state. */
198 void unscheduleActivateThreadEvent(int tid)
199 {
200 if (activateThreadEvent[tid].scheduled())
201 activateThreadEvent[tid].squash();
202 }
203
103 typedef O3ThreadState<Impl> Thread;
104
105 typedef typename std::list<DynInstPtr>::iterator ListIt;
106
107 friend class O3ThreadContext<Impl>;
108
109 public:
110 enum Status {

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197
198 /** Unschedule actiavte thread event, regardless of its current state. */
199 void unscheduleActivateThreadEvent(int tid)
200 {
201 if (activateThreadEvent[tid].scheduled())
202 activateThreadEvent[tid].squash();
203 }
204
205#if !FULL_SYSTEM
206 TheISA::IntReg getSyscallArg(int i, int tid);
207
208 /** Used to shift args for indirect syscall. */
209 void setSyscallArg(int i, TheISA::IntReg val, int tid);
210#endif
211
204 /** The tick event used for scheduling CPU ticks. */
205 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
206
207 class DeallocateContextEvent : public Event
208 {
209 private:
210 /** Number of Thread to deactivate */
211 int tid;

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252 deallocateContextEvent[tid].squash();
253 }
254
255 /** The tick event used for scheduling CPU ticks. */
256 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
257
258 public:
259 /** Constructs a CPU with the given parameters. */
212 /** The tick event used for scheduling CPU ticks. */
213 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
214
215 class DeallocateContextEvent : public Event
216 {
217 private:
218 /** Number of Thread to deactivate */
219 int tid;

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260 deallocateContextEvent[tid].squash();
261 }
262
263 /** The tick event used for scheduling CPU ticks. */
264 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
265
266 public:
267 /** Constructs a CPU with the given parameters. */
260 FullO3CPU(O3CPU *o3_cpu, DerivO3CPUParams *params);
268 FullO3CPU(DerivO3CPUParams *params);
261 /** Destructor. */
262 ~FullO3CPU();
263
264 /** Registers statistics. */
269 /** Destructor. */
270 ~FullO3CPU();
271
272 /** Registers statistics. */
265 void fullCPURegStats();
273 void regStats();
266
267 void demapPage(Addr vaddr, uint64_t asn)
268 {
269 this->itb->demapPage(vaddr, asn);
270 this->dtb->demapPage(vaddr, asn);
271 }
272
273 void demapInstPage(Addr vaddr, uint64_t asn)

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363
364 /** Serialize state. */
365 virtual void serialize(std::ostream &os);
366
367 /** Unserialize from a checkpoint. */
368 virtual void unserialize(Checkpoint *cp, const std::string &section);
369
370 public:
274
275 void demapPage(Addr vaddr, uint64_t asn)
276 {
277 this->itb->demapPage(vaddr, asn);
278 this->dtb->demapPage(vaddr, asn);
279 }
280
281 void demapInstPage(Addr vaddr, uint64_t asn)

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371
372 /** Serialize state. */
373 virtual void serialize(std::ostream &os);
374
375 /** Unserialize from a checkpoint. */
376 virtual void unserialize(Checkpoint *cp, const std::string &section);
377
378 public:
371 /** Executes a syscall on this cycle.
372 * ---------------------------------------
373 * Note: this is a virtual function. CPU-Specific
374 * functionality defined in derived classes
379#if !FULL_SYSTEM
380 /** Executes a syscall.
381 * @todo: Determine if this needs to be virtual.
375 */
382 */
376 virtual void syscall(int tid) { panic("Unimplemented!"); }
383 void syscall(int64_t callnum, int tid);
377
384
385 /** Sets the return value of a syscall. */
386 void setSyscallReturn(SyscallReturn return_value, int tid);
387
388#endif
389
378 /** Starts draining the CPU's pipeline of all instructions in
379 * order to stop all memory accesses. */
380 virtual unsigned int drain(Event *drain_event);
381
382 /** Resumes execution after a drain. */
383 virtual void resume();
384
385 /** Signals to this CPU that a stage has completed switching out. */

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390
391 /** Takes over from another CPU. */
392 virtual void takeOverFrom(BaseCPU *oldCPU);
393
394 /** Get the current instruction sequence number, and increment it. */
395 InstSeqNum getAndIncrementInstSeq()
396 { return globalSeqNum++; }
397
390 /** Starts draining the CPU's pipeline of all instructions in
391 * order to stop all memory accesses. */
392 virtual unsigned int drain(Event *drain_event);
393
394 /** Resumes execution after a drain. */
395 virtual void resume();
396
397 /** Signals to this CPU that a stage has completed switching out. */

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402
403 /** Takes over from another CPU. */
404 virtual void takeOverFrom(BaseCPU *oldCPU);
405
406 /** Get the current instruction sequence number, and increment it. */
407 InstSeqNum getAndIncrementInstSeq()
408 { return globalSeqNum++; }
409
410 /** Traps to handle given fault. */
411 void trap(Fault fault, unsigned tid);
412
398#if FULL_SYSTEM
413#if FULL_SYSTEM
414 /** Posts an interrupt. */
415 void post_interrupt(int int_num, int index);
416
417 /** HW return from error interrupt. */
418 Fault hwrei(unsigned tid);
419
420 bool simPalCheck(int palFunc, unsigned tid);
421
422 /** Returns the Fault for any valid interrupt. */
423 Fault getInterrupts();
424
425 /** Processes any an interrupt fault. */
426 void processInterrupts(Fault interrupt);
427
428 /** Halts the CPU. */
429 void halt() { panic("Halt not implemented!\n"); }
430
399 /** Update the Virt and Phys ports of all ThreadContexts to
400 * reflect change in memory connections. */
401 void updateMemPorts();
402
403 /** Check if this address is a valid instruction address. */
404 bool validInstAddr(Addr addr) { return true; }
405
406 /** Check if this address is a valid data address. */

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420
421 /** Get data asid. */
422 int getDataAsid(unsigned tid)
423 { return thread[tid]->getDataAsid(); }
424
425#endif
426
427 /** Register accessors. Index refers to the physical register index. */
431 /** Update the Virt and Phys ports of all ThreadContexts to
432 * reflect change in memory connections. */
433 void updateMemPorts();
434
435 /** Check if this address is a valid instruction address. */
436 bool validInstAddr(Addr addr) { return true; }
437
438 /** Check if this address is a valid data address. */

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452
453 /** Get data asid. */
454 int getDataAsid(unsigned tid)
455 { return thread[tid]->getDataAsid(); }
456
457#endif
458
459 /** Register accessors. Index refers to the physical register index. */
460
461 /** Reads a miscellaneous register. */
462 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid);
463
464 /** Reads a misc. register, including any side effects the read
465 * might have as defined by the architecture.
466 */
467 TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
468
469 /** Sets a miscellaneous register. */
470 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
471
472 /** Sets a misc. register, including any side effects the write
473 * might have as defined by the architecture.
474 */
475 void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
476 unsigned tid);
477
428 uint64_t readIntReg(int reg_idx);
429
430 TheISA::FloatReg readFloatReg(int reg_idx);
431
432 TheISA::FloatReg readFloatReg(int reg_idx, int width);
433
434 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
435

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491 void setNextNPC(Addr val, unsigned tid);
492
493 /** Reads the commit next micro PC of a specific thread. */
494 Addr readNextMicroPC(unsigned tid);
495
496 /** Sets the commit next micro PC of a specific thread. */
497 void setNextMicroPC(Addr val, unsigned tid);
498
478 uint64_t readIntReg(int reg_idx);
479
480 TheISA::FloatReg readFloatReg(int reg_idx);
481
482 TheISA::FloatReg readFloatReg(int reg_idx, int width);
483
484 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
485

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541 void setNextNPC(Addr val, unsigned tid);
542
543 /** Reads the commit next micro PC of a specific thread. */
544 Addr readNextMicroPC(unsigned tid);
545
546 /** Sets the commit next micro PC of a specific thread. */
547 void setNextMicroPC(Addr val, unsigned tid);
548
549 /** Initiates a squash of all in-flight instructions for a given
550 * thread. The source of the squash is an external update of
551 * state through the TC.
552 */
553 void squashFromTC(unsigned tid);
554
499 /** Function to add instruction onto the head of the list of the
500 * instructions. Used when new instructions are fetched.
501 */
502 ListIt addInst(DynInstPtr &inst);
503
504 /** Function to tell the CPU that an instruction has completed. */
505 void instDone(unsigned tid);
506

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706 unsigned numThreads;
707
708 /** Mapping for system thread id to cpu id */
709 std::map<unsigned,unsigned> threadMap;
710
711 /** Available thread ids in the cpu*/
712 std::vector<unsigned> tids;
713
555 /** Function to add instruction onto the head of the list of the
556 * instructions. Used when new instructions are fetched.
557 */
558 ListIt addInst(DynInstPtr &inst);
559
560 /** Function to tell the CPU that an instruction has completed. */
561 void instDone(unsigned tid);
562

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762 unsigned numThreads;
763
764 /** Mapping for system thread id to cpu id */
765 std::map<unsigned,unsigned> threadMap;
766
767 /** Available thread ids in the cpu*/
768 std::vector<unsigned> tids;
769
770 /** CPU read function, forwards read to LSQ. */
771 template <class T>
772 Fault read(RequestPtr &req, T &data, int load_idx)
773 {
774 return this->iew.ldstQueue.read(req, data, load_idx);
775 }
776
777 /** CPU write function, forwards write to LSQ. */
778 template <class T>
779 Fault write(RequestPtr &req, T &data, int store_idx)
780 {
781 return this->iew.ldstQueue.write(req, data, store_idx);
782 }
783
784 Addr lockAddr;
785
786 /** Temporary fix for the lock flag, works in the UP case. */
787 bool lockFlag;
788
714 /** Stat for total number of times the CPU is descheduled. */
715 Stats::Scalar<> timesIdled;
716 /** Stat for total number of cycles the CPU spends descheduled. */
717 Stats::Scalar<> idleCycles;
718 /** Stat for the number of committed instructions per thread. */
719 Stats::Vector<> committedInsts;
720 /** Stat for the total number of committed instructions. */
721 Stats::Scalar<> totalCommittedInsts;
722 /** Stat for the CPI per thread. */
723 Stats::Formula cpi;
724 /** Stat for the total CPI. */
725 Stats::Formula totalCpi;
726 /** Stat for the IPC per thread. */
727 Stats::Formula ipc;
728 /** Stat for the total IPC. */
729 Stats::Formula totalIpc;
730};
731
732#endif // __CPU_O3_CPU_HH__
789 /** Stat for total number of times the CPU is descheduled. */
790 Stats::Scalar<> timesIdled;
791 /** Stat for total number of cycles the CPU spends descheduled. */
792 Stats::Scalar<> idleCycles;
793 /** Stat for the number of committed instructions per thread. */
794 Stats::Vector<> committedInsts;
795 /** Stat for the total number of committed instructions. */
796 Stats::Scalar<> totalCommittedInsts;
797 /** Stat for the CPI per thread. */
798 Stats::Formula cpi;
799 /** Stat for the total CPI. */
800 Stats::Formula totalCpi;
801 /** Stat for the IPC per thread. */
802 Stats::Formula ipc;
803 /** Stat for the total IPC. */
804 Stats::Formula totalIpc;
805};
806
807#endif // __CPU_O3_CPU_HH__