cpu.hh (3402:db60546818d0) cpu.hh (3781:b00795985f07)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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86 * FullO3CPU class, has each of the stages (fetch through commit)
87 * within it, as well as all of the time buffers between stages. The
88 * tick() function for the CPU is defined here.
89 */
90template <class Impl>
91class FullO3CPU : public BaseO3CPU
92{
93 public:
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 77 unchanged lines hidden (view full) ---

86 * FullO3CPU class, has each of the stages (fetch through commit)
87 * within it, as well as all of the time buffers between stages. The
88 * tick() function for the CPU is defined here.
89 */
90template <class Impl>
91class FullO3CPU : public BaseO3CPU
92{
93 public:
94 typedef TheISA::FloatReg FloatReg;
95 typedef TheISA::FloatRegBits FloatRegBits;
96
97 // Typedefs from the Impl here.
98 typedef typename Impl::CPUPol CPUPolicy;
99 typedef typename Impl::Params Params;
100 typedef typename Impl::DynInstPtr DynInstPtr;
101
102 typedef O3ThreadState<Impl> Thread;
103
104 typedef typename std::list<DynInstPtr>::iterator ListIt;

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109 enum Status {
110 Running,
111 Idle,
112 Halted,
113 Blocked,
114 SwitchedOut
115 };
116
94 // Typedefs from the Impl here.
95 typedef typename Impl::CPUPol CPUPolicy;
96 typedef typename Impl::Params Params;
97 typedef typename Impl::DynInstPtr DynInstPtr;
98
99 typedef O3ThreadState<Impl> Thread;
100
101 typedef typename std::list<DynInstPtr>::iterator ListIt;

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106 enum Status {
107 Running,
108 Idle,
109 Halted,
110 Blocked,
111 SwitchedOut
112 };
113
114#if FULL_SYSTEM
115 TheISA::ITB * itb;
116 TheISA::DTB * dtb;
117#endif
118
117 /** Overall CPU status. */
118 Status _status;
119
120 /** Per-thread status in CPU, used for SMT. */
121 Status _threadStatus[Impl::MaxThreads];
122
123 private:
124 class TickEvent : public Event

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377 int getDataAsid(unsigned tid)
378 { return thread[tid]->getDataAsid(); }
379
380#endif
381
382 /** Register accessors. Index refers to the physical register index. */
383 uint64_t readIntReg(int reg_idx);
384
119 /** Overall CPU status. */
120 Status _status;
121
122 /** Per-thread status in CPU, used for SMT. */
123 Status _threadStatus[Impl::MaxThreads];
124
125 private:
126 class TickEvent : public Event

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379 int getDataAsid(unsigned tid)
380 { return thread[tid]->getDataAsid(); }
381
382#endif
383
384 /** Register accessors. Index refers to the physical register index. */
385 uint64_t readIntReg(int reg_idx);
386
385 FloatReg readFloatReg(int reg_idx);
387 TheISA::FloatReg readFloatReg(int reg_idx);
386
388
387 FloatReg readFloatReg(int reg_idx, int width);
389 TheISA::FloatReg readFloatReg(int reg_idx, int width);
388
390
389 FloatRegBits readFloatRegBits(int reg_idx);
391 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
390
392
391 FloatRegBits readFloatRegBits(int reg_idx, int width);
393 TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width);
392
393 void setIntReg(int reg_idx, uint64_t val);
394
394
395 void setIntReg(int reg_idx, uint64_t val);
396
395 void setFloatReg(int reg_idx, FloatReg val);
397 void setFloatReg(int reg_idx, TheISA::FloatReg val);
396
398
397 void setFloatReg(int reg_idx, FloatReg val, int width);
399 void setFloatReg(int reg_idx, TheISA::FloatReg val, int width);
398
400
399 void setFloatRegBits(int reg_idx, FloatRegBits val);
401 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
400
402
401 void setFloatRegBits(int reg_idx, FloatRegBits val, int width);
403 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width);
402
403 uint64_t readArchIntReg(int reg_idx, unsigned tid);
404
405 float readArchFloatRegSingle(int reg_idx, unsigned tid);
406
407 double readArchFloatRegDouble(int reg_idx, unsigned tid);
408
409 uint64_t readArchFloatRegInt(int reg_idx, unsigned tid);

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405 uint64_t readArchIntReg(int reg_idx, unsigned tid);
406
407 float readArchFloatRegSingle(int reg_idx, unsigned tid);
408
409 double readArchFloatRegDouble(int reg_idx, unsigned tid);
410
411 uint64_t readArchFloatRegInt(int reg_idx, unsigned tid);

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