cpu.hh (2875:9b6f6b75b187) cpu.hh (2876:a862ab9f93f8)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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52//#include "cpu/o3/thread_context.hh"
53#include "sim/process.hh"
54
55template <class>
56class Checker;
57class ThreadContext;
58template <class>
59class O3ThreadContext;
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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52//#include "cpu/o3/thread_context.hh"
53#include "sim/process.hh"
54
55template <class>
56class Checker;
57class ThreadContext;
58template <class>
59class O3ThreadContext;
60
61class Checkpoint;
60class MemObject;
61class Process;
62
63class BaseO3CPU : public BaseCPU
64{
65 //Stuff that's pretty ISA independent will go here.
66 public:
67 typedef BaseCPU::Params Params;

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104 friend class O3ThreadContext<Impl>;
105
106 public:
107 enum Status {
108 Running,
109 Idle,
110 Halted,
111 Blocked,
62class MemObject;
63class Process;
64
65class BaseO3CPU : public BaseCPU
66{
67 //Stuff that's pretty ISA independent will go here.
68 public:
69 typedef BaseCPU::Params Params;

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106 friend class O3ThreadContext<Impl>;
107
108 public:
109 enum Status {
110 Running,
111 Idle,
112 Halted,
113 Blocked,
114 Drained,
112 SwitchedOut
113 };
114
115 /** Overall CPU status. */
116 Status _status;
117
118 /** Per-thread status in CPU, used for SMT. */
119 Status _threadStatus[Impl::MaxThreads];

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311
312 /** Executes a syscall on this cycle.
313 * ---------------------------------------
314 * Note: this is a virtual function. CPU-Specific
315 * functionality defined in derived classes
316 */
317 virtual void syscall(int tid) { panic("Unimplemented!"); }
318
115 SwitchedOut
116 };
117
118 /** Overall CPU status. */
119 Status _status;
120
121 /** Per-thread status in CPU, used for SMT. */
122 Status _threadStatus[Impl::MaxThreads];

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314
315 /** Executes a syscall on this cycle.
316 * ---------------------------------------
317 * Note: this is a virtual function. CPU-Specific
318 * functionality defined in derived classes
319 */
320 virtual void syscall(int tid) { panic("Unimplemented!"); }
321
319 /** Switches out this CPU. */
320 void switchOut();
322 /** Starts draining the CPU's pipeline of all instructions in
323 * order to stop all memory accesses. */
324 virtual bool drain(Event *drain_event);
321
325
326 /** Resumes execution after a drain. */
327 virtual void resume();
328
322 /** Signals to this CPU that a stage has completed switching out. */
329 /** Signals to this CPU that a stage has completed switching out. */
323 void signalSwitched();
330 void signalDrained();
324
331
332 /** Switches out this CPU. */
333 virtual void switchOut();
334
325 /** Takes over from another CPU. */
335 /** Takes over from another CPU. */
326 void takeOverFrom(BaseCPU *oldCPU);
336 virtual void takeOverFrom(BaseCPU *oldCPU);
327
328 /** Get the current instruction sequence number, and increment it. */
329 InstSeqNum getAndIncrementInstSeq()
330 { return globalSeqNum++; }
331
332#if FULL_SYSTEM
333 /** Check if this address is a valid instruction address. */
334 bool validInstAddr(Addr addr) { return true; }

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591
592 /** Pointer to physical memory. */
593 PhysicalMemory *physmem;
594#endif
595
596 /** Pointer to memory. */
597 MemObject *mem;
598
337
338 /** Get the current instruction sequence number, and increment it. */
339 InstSeqNum getAndIncrementInstSeq()
340 { return globalSeqNum++; }
341
342#if FULL_SYSTEM
343 /** Check if this address is a valid instruction address. */
344 bool validInstAddr(Addr addr) { return true; }

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601
602 /** Pointer to physical memory. */
603 PhysicalMemory *physmem;
604#endif
605
606 /** Pointer to memory. */
607 MemObject *mem;
608
599 /** Counter of how many stages have completed switching out. */
600 int switchCount;
609 /** Event to call process() on once draining has completed. */
610 Event *drainEvent;
601
611
612 /** Counter of how many stages have completed draining. */
613 int drainCount;
614
602 /** Pointers to all of the threads in the CPU. */
603 std::vector<Thread *> thread;
604
605 /** Pointer to the icache interface. */
606 MemInterface *icacheInterface;
607 /** Pointer to the dcache interface. */
608 MemInterface *dcacheInterface;
609

--- 43 unchanged lines hidden --- 		615 /** Pointers to all of the threads in the CPU. */
616 std::vector<Thread *> thread;
617
618 /** Pointer to the icache interface. */
619 MemInterface *icacheInterface;
620 /** Pointer to the dcache interface. */
621 MemInterface *dcacheInterface;
622

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