cpu.hh (2871:7ed5c9ef3eb6) cpu.hh (2875:9b6f6b75b187)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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52//#include "cpu/o3/thread_context.hh"
53#include "sim/process.hh"
54
55template <class>
56class Checker;
57class ThreadContext;
58template <class>
59class O3ThreadContext;
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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52//#include "cpu/o3/thread_context.hh"
53#include "sim/process.hh"
54
55template <class>
56class Checker;
57class ThreadContext;
58template <class>
59class O3ThreadContext;
60
61class Checkpoint;
62class MemObject;
63class Process;
64
65class BaseO3CPU : public BaseCPU
66{
67 //Stuff that's pretty ISA independent will go here.
68 public:
69 typedef BaseCPU::Params Params;

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194 {
195 if (activateThreadEvent[tid].scheduled())
196 activateThreadEvent[tid].squash();
197 }
198
199 /** The tick event used for scheduling CPU ticks. */
200 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
201
60class MemObject;
61class Process;
62
63class BaseO3CPU : public BaseCPU
64{
65 //Stuff that's pretty ISA independent will go here.
66 public:
67 typedef BaseCPU::Params Params;

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192 {
193 if (activateThreadEvent[tid].scheduled())
194 activateThreadEvent[tid].squash();
195 }
196
197 /** The tick event used for scheduling CPU ticks. */
198 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
199
200 class DeallocateContextEvent : public Event
201 {
202 private:
203 /** Number of Thread to Activate */
204 int tid;
205
206 /** Pointer to the CPU. */
207 FullO3CPU<Impl> *cpu;
208
209 public:
210 /** Constructs the event. */
211 DeallocateContextEvent();
212
213 /** Initialize Event */
214 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
215
216 /** Processes the event, calling activateThread() on the CPU. */
217 void process();
218
219 /** Returns the description of the event. */
220 const char *description();
221 };
222
223 /** Schedule cpu to deallocate thread context.*/
224 void scheduleDeallocateContextEvent(int tid, int delay)
225 {
226 // Schedule thread to activate, regardless of its current state.
227 if (deallocateContextEvent[tid].squashed())
228 deallocateContextEvent[tid].reschedule(curTick + cycles(delay));
229 else if (!deallocateContextEvent[tid].scheduled())
230 deallocateContextEvent[tid].schedule(curTick + cycles(delay));
231 }
232
233 /** Unschedule thread deallocation in CPU */
234 void unscheduleDeallocateContextEvent(int tid)
235 {
236 if (deallocateContextEvent[tid].scheduled())
237 deallocateContextEvent[tid].squash();
238 }
239
240 /** The tick event used for scheduling CPU ticks. */
241 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
242
202 public:
203 /** Constructs a CPU with the given parameters. */
204 FullO3CPU(Params *params);
205 /** Destructor. */
206 ~FullO3CPU();
207
208 /** Registers statistics. */
209 void fullCPURegStats();
210
243 public:
244 /** Constructs a CPU with the given parameters. */
245 FullO3CPU(Params *params);
246 /** Destructor. */
247 ~FullO3CPU();
248
249 /** Registers statistics. */
250 void fullCPURegStats();
251
211 /** Returns a specific port. */
212 Port *getPort(const std::string &if_name, int idx);
213
214 /** Ticks CPU, calling tick() on each stage, and checking the overall
215 * activity to see if the CPU should deschedule itself.
216 */
217 void tick();
218
219 /** Initialize the CPU */
220 void init();
221
222 /** Returns the Number of Active Threads in the CPU */
223 int numActiveThreads()
224 { return activeThreads.size(); }
225
226 /** Add Thread to Active Threads List */
252 /** Ticks CPU, calling tick() on each stage, and checking the overall
253 * activity to see if the CPU should deschedule itself.
254 */
255 void tick();
256
257 /** Initialize the CPU */
258 void init();
259
260 /** Returns the Number of Active Threads in the CPU */
261 int numActiveThreads()
262 { return activeThreads.size(); }
263
264 /** Add Thread to Active Threads List */
227 void activateThread(unsigned int tid);
265 void activateThread(unsigned tid);
228
266
267 /** Remove Thread from Active Threads List */
268 void deactivateThread(unsigned tid);
269
229 /** Setup CPU to insert a thread's context */
230 void insertThread(unsigned tid);
231
232 /** Remove all of a thread's context from CPU */
233 void removeThread(unsigned tid);
234
235 /** Count the Total Instructions Committed in the CPU. */
236 virtual Counter totalInstructions() const

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247 void activateContext(int tid, int delay);
248
249 /** Remove Thread from Active Threads List */
250 void suspendContext(int tid);
251
252 /** Remove Thread from Active Threads List &&
253 * Remove Thread Context from CPU.
254 */
270 /** Setup CPU to insert a thread's context */
271 void insertThread(unsigned tid);
272
273 /** Remove all of a thread's context from CPU */
274 void removeThread(unsigned tid);
275
276 /** Count the Total Instructions Committed in the CPU. */
277 virtual Counter totalInstructions() const

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288 void activateContext(int tid, int delay);
289
290 /** Remove Thread from Active Threads List */
291 void suspendContext(int tid);
292
293 /** Remove Thread from Active Threads List &&
294 * Remove Thread Context from CPU.
295 */
255 void deallocateContext(int tid);
296 void deallocateContext(int tid, int delay = 1);
256
257 /** Remove Thread from Active Threads List &&
258 * Remove Thread Context from CPU.
259 */
260 void haltContext(int tid);
261
262 /** Activate a Thread When CPU Resources are Available. */
263 void activateWhenReady(int tid);
264
265 /** Add or Remove a Thread Context in the CPU. */
266 void doContextSwitch();
267
268 /** Update The Order In Which We Process Threads. */
269 void updateThreadPriority();
270
297
298 /** Remove Thread from Active Threads List &&
299 * Remove Thread Context from CPU.
300 */
301 void haltContext(int tid);
302
303 /** Activate a Thread When CPU Resources are Available. */
304 void activateWhenReady(int tid);
305
306 /** Add or Remove a Thread Context in the CPU. */
307 void doContextSwitch();
308
309 /** Update The Order In Which We Process Threads. */
310 void updateThreadPriority();
311
271 /** Serialize state. */
272 virtual void serialize(std::ostream &os);
273
274 /** Unserialize from a checkpoint. */
275 virtual void unserialize(Checkpoint *cp, const std::string &section);
276
277 public:
278 /** Executes a syscall on this cycle.
279 * ---------------------------------------
280 * Note: this is a virtual function. CPU-Specific
281 * functionality defined in derived classes
282 */
283 virtual void syscall(int tid) { panic("Unimplemented!"); }
284
312 /** Executes a syscall on this cycle.
313 * ---------------------------------------
314 * Note: this is a virtual function. CPU-Specific
315 * functionality defined in derived classes
316 */
317 virtual void syscall(int tid) { panic("Unimplemented!"); }
318
285 /** Starts draining the CPU's pipeline of all instructions in
286 * order to stop all memory accesses. */
287 virtual bool drain(Event *drain_event);
319 /** Switches out this CPU. */
320 void switchOut();
288
321
289 /** Resumes execution after a drain. */
290 virtual void resume();
291
292 /** Signals to this CPU that a stage has completed switching out. */
322 /** Signals to this CPU that a stage has completed switching out. */
293 void signalDrained();
323 void signalSwitched();
294
324
295 /** Switches out this CPU. */
296 virtual void switchOut();
297
298 /** Takes over from another CPU. */
325 /** Takes over from another CPU. */
299 virtual void takeOverFrom(BaseCPU *oldCPU);
326 void takeOverFrom(BaseCPU *oldCPU);
300
301 /** Get the current instruction sequence number, and increment it. */
302 InstSeqNum getAndIncrementInstSeq()
303 { return globalSeqNum++; }
304
305#if FULL_SYSTEM
306 /** Check if this address is a valid instruction address. */
307 bool validInstAddr(Addr addr) { return true; }

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564
565 /** Pointer to physical memory. */
566 PhysicalMemory *physmem;
567#endif
568
569 /** Pointer to memory. */
570 MemObject *mem;
571
327
328 /** Get the current instruction sequence number, and increment it. */
329 InstSeqNum getAndIncrementInstSeq()
330 { return globalSeqNum++; }
331
332#if FULL_SYSTEM
333 /** Check if this address is a valid instruction address. */
334 bool validInstAddr(Addr addr) { return true; }

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591
592 /** Pointer to physical memory. */
593 PhysicalMemory *physmem;
594#endif
595
596 /** Pointer to memory. */
597 MemObject *mem;
598
572 /** Event to call process() on once draining has completed. */
573 Event *drainEvent;
599 /** Counter of how many stages have completed switching out. */
600 int switchCount;
574
601
575 /** Counter of how many stages have completed draining. */
576 int drainCount;
577
578 /** Pointers to all of the threads in the CPU. */
579 std::vector<Thread *> thread;
580
581 /** Pointer to the icache interface. */
582 MemInterface *icacheInterface;
583 /** Pointer to the dcache interface. */
584 MemInterface *dcacheInterface;
585

--- 43 unchanged lines hidden --- 		602 /** Pointers to all of the threads in the CPU. */
603 std::vector<Thread *> thread;
604
605 /** Pointer to the icache interface. */
606 MemInterface *icacheInterface;
607 /** Pointer to the dcache interface. */
608 MemInterface *dcacheInterface;
609

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