cpu.hh (2840:227f7c4f8c81) | cpu.hh (2843:19c4c6c2b5b1) |
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1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 43 unchanged lines hidden (view full) --- 52//#include "cpu/o3/thread_context.hh" 53#include "sim/process.hh" 54 55template <class> 56class Checker; 57class ThreadContext; 58template <class> 59class O3ThreadContext; | 1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 43 unchanged lines hidden (view full) --- 52//#include "cpu/o3/thread_context.hh" 53#include "sim/process.hh" 54 55template <class> 56class Checker; 57class ThreadContext; 58template <class> 59class O3ThreadContext; |
60 61class Checkpoint; |
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60class MemObject; 61class Process; 62 63class BaseO3CPU : public BaseCPU 64{ 65 //Stuff that's pretty ISA independent will go here. 66 public: 67 typedef BaseCPU::Params Params; --- 36 unchanged lines hidden (view full) --- 104 friend class O3ThreadContext<Impl>; 105 106 public: 107 enum Status { 108 Running, 109 Idle, 110 Halted, 111 Blocked, | 62class MemObject; 63class Process; 64 65class BaseO3CPU : public BaseCPU 66{ 67 //Stuff that's pretty ISA independent will go here. 68 public: 69 typedef BaseCPU::Params Params; --- 36 unchanged lines hidden (view full) --- 106 friend class O3ThreadContext<Impl>; 107 108 public: 109 enum Status { 110 Running, 111 Idle, 112 Halted, 113 Blocked, |
114 Drained, |
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112 SwitchedOut 113 }; 114 115 /** Overall CPU status. */ 116 Status _status; 117 118 /** Per-thread status in CPU, used for SMT. */ 119 Status _threadStatus[Impl::MaxThreads]; --- 145 unchanged lines hidden (view full) --- 265 266 /** Executes a syscall on this cycle. 267 * --------------------------------------- 268 * Note: this is a virtual function. CPU-Specific 269 * functionality defined in derived classes 270 */ 271 virtual void syscall(int tid) { panic("Unimplemented!"); } 272 | 115 SwitchedOut 116 }; 117 118 /** Overall CPU status. */ 119 Status _status; 120 121 /** Per-thread status in CPU, used for SMT. */ 122 Status _threadStatus[Impl::MaxThreads]; --- 145 unchanged lines hidden (view full) --- 268 269 /** Executes a syscall on this cycle. 270 * --------------------------------------- 271 * Note: this is a virtual function. CPU-Specific 272 * functionality defined in derived classes 273 */ 274 virtual void syscall(int tid) { panic("Unimplemented!"); } 275 |
273 /** Switches out this CPU. */ 274 void switchOut(); | 276 /** Starts draining the CPU's pipeline of all instructions in 277 * order to stop all memory accesses. */ 278 virtual bool drain(Event *drain_event); |
275 | 279 |
280 /** Resumes execution after a drain. */ 281 virtual void resume(); 282 |
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276 /** Signals to this CPU that a stage has completed switching out. */ | 283 /** Signals to this CPU that a stage has completed switching out. */ |
277 void signalSwitched(); | 284 void signalDrained(); |
278 | 285 |
286 /** Switches out this CPU. */ 287 virtual void switchOut(); 288 |
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279 /** Takes over from another CPU. */ | 289 /** Takes over from another CPU. */ |
280 void takeOverFrom(BaseCPU *oldCPU); | 290 virtual void takeOverFrom(BaseCPU *oldCPU); |
281 282 /** Get the current instruction sequence number, and increment it. */ 283 InstSeqNum getAndIncrementInstSeq() 284 { return globalSeqNum++; } 285 286#if FULL_SYSTEM 287 /** Check if this address is a valid instruction address. */ 288 bool validInstAddr(Addr addr) { return true; } --- 256 unchanged lines hidden (view full) --- 545 546 /** Pointer to physical memory. */ 547 PhysicalMemory *physmem; 548#endif 549 550 /** Pointer to memory. */ 551 MemObject *mem; 552 | 291 292 /** Get the current instruction sequence number, and increment it. */ 293 InstSeqNum getAndIncrementInstSeq() 294 { return globalSeqNum++; } 295 296#if FULL_SYSTEM 297 /** Check if this address is a valid instruction address. */ 298 bool validInstAddr(Addr addr) { return true; } --- 256 unchanged lines hidden (view full) --- 555 556 /** Pointer to physical memory. */ 557 PhysicalMemory *physmem; 558#endif 559 560 /** Pointer to memory. */ 561 MemObject *mem; 562 |
553 /** Counter of how many stages have completed switching out. */ 554 int switchCount; | 563 /** Event to call process() on once draining has completed. */ 564 Event *drainEvent; |
555 | 565 |
566 /** Counter of how many stages have completed draining. */ 567 int drainCount; 568 |
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556 /** Pointers to all of the threads in the CPU. */ 557 std::vector<Thread *> thread; 558 559 /** Pointer to the icache interface. */ 560 MemInterface *icacheInterface; 561 /** Pointer to the dcache interface. */ 562 MemInterface *dcacheInterface; 563 --- 43 unchanged lines hidden --- | 569 /** Pointers to all of the threads in the CPU. */ 570 std::vector<Thread *> thread; 571 572 /** Pointer to the icache interface. */ 573 MemInterface *icacheInterface; 574 /** Pointer to the dcache interface. */ 575 MemInterface *dcacheInterface; 576 --- 43 unchanged lines hidden --- |