cpu.hh (2733:e0eac8fc5774) cpu.hh (2756:7bf0d6481df9)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
29 */
30
31#ifndef __CPU_O3_CPU_HH__
32#define __CPU_O3_CPU_HH__
33
34#include <iostream>
35#include <list>
36#include <queue>

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51#include "sim/process.hh"
52
53template <class>
54class Checker;
55class ThreadContext;
56class MemObject;
57class Process;
58
30 */
31
32#ifndef __CPU_O3_CPU_HH__
33#define __CPU_O3_CPU_HH__
34
35#include <iostream>
36#include <list>
37#include <queue>

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52#include "sim/process.hh"
53
54template <class>
55class Checker;
56class ThreadContext;
57class MemObject;
58class Process;
59
59class BaseO3CPU : public BaseCPU
60class BaseFullCPU : public BaseCPU
60{
61 //Stuff that's pretty ISA independent will go here.
62 public:
63 typedef BaseCPU::Params Params;
64
61{
62 //Stuff that's pretty ISA independent will go here.
63 public:
64 typedef BaseCPU::Params Params;
65
65 BaseO3CPU(Params *params);
66 BaseFullCPU(Params *params);
66
67 void regStats();
68
69 int readCpuId() { return cpu_id; }
70
71 protected:
72 int cpu_id;
73};
74
75/**
76 * FullO3CPU class, has each of the stages (fetch through commit)
77 * within it, as well as all of the time buffers between stages. The
78 * tick() function for the CPU is defined here.
79 */
80template <class Impl>
67
68 void regStats();
69
70 int readCpuId() { return cpu_id; }
71
72 protected:
73 int cpu_id;
74};
75
76/**
77 * FullO3CPU class, has each of the stages (fetch through commit)
78 * within it, as well as all of the time buffers between stages. The
79 * tick() function for the CPU is defined here.
80 */
81template <class Impl>
81class FullO3CPU : public BaseO3CPU
82class FullO3CPU : public BaseFullCPU
82{
83 public:
84 typedef TheISA::FloatReg FloatReg;
85 typedef TheISA::FloatRegBits FloatRegBits;
86
87 // Typedefs from the Impl here.
88 typedef typename Impl::CPUPol CPUPolicy;
89 typedef typename Impl::Params Params;

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294 void setPC(Addr new_PC, unsigned tid);
295
296 /** Reads the next PC of a specific thread. */
297 uint64_t readNextPC(unsigned tid);
298
299 /** Sets the next PC of a specific thread. */
300 void setNextPC(uint64_t val, unsigned tid);
301
83{
84 public:
85 typedef TheISA::FloatReg FloatReg;
86 typedef TheISA::FloatRegBits FloatRegBits;
87
88 // Typedefs from the Impl here.
89 typedef typename Impl::CPUPol CPUPolicy;
90 typedef typename Impl::Params Params;

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295 void setPC(Addr new_PC, unsigned tid);
296
297 /** Reads the next PC of a specific thread. */
298 uint64_t readNextPC(unsigned tid);
299
300 /** Sets the next PC of a specific thread. */
301 void setNextPC(uint64_t val, unsigned tid);
302
303 /** Reads the next NPC of a specific thread. */
304 uint64_t readNextNPC(unsigned tid);
305
306 /** Sets the next NPC of a specific thread. */
307 void setNextNPC(uint64_t val, unsigned tid);
308
302 /** Function to add instruction onto the head of the list of the
303 * instructions. Used when new instructions are fetched.
304 */
305 ListIt addInst(DynInstPtr &inst);
306
307 /** Function to tell the CPU that an instruction has completed. */
308 void instDone(unsigned tid);
309

--- 228 unchanged lines hidden --- 		309 /** Function to add instruction onto the head of the list of the
310 * instructions. Used when new instructions are fetched.
311 */
312 ListIt addInst(DynInstPtr &inst);
313
314 /** Function to tell the CPU that an instruction has completed. */
315 void instDone(unsigned tid);
316

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