cpu.hh (2690:f4337c0d9e6f) cpu.hh (2698:d5f35d41e017)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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485 Sampler *sampler;
486
487 /** Counter of how many stages have completed switching out. */
488 int switchCount;
489
490 /** Pointers to all of the threads in the CPU. */
491 std::vector<Thread *> thread;
492
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 476 unchanged lines hidden (view full) ---

485 Sampler *sampler;
486
487 /** Counter of how many stages have completed switching out. */
488 int switchCount;
489
490 /** Pointers to all of the threads in the CPU. */
491 std::vector<Thread *> thread;
492
493#if 0
494 /** Page table pointer. */
495 PageTable *pTable;
496#endif
497
498 /** Pointer to the icache interface. */
499 MemInterface *icacheInterface;
500 /** Pointer to the dcache interface. */
501 MemInterface *dcacheInterface;
502
503 /** Whether or not the CPU should defer its registration. */
504 bool deferRegistration;
505

--- 37 unchanged lines hidden --- 		493 /** Pointer to the icache interface. */
494 MemInterface *icacheInterface;
495 /** Pointer to the dcache interface. */
496 MemInterface *dcacheInterface;
497
498 /** Whether or not the CPU should defer its registration. */
499 bool deferRegistration;
500

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