cpu.hh (2665:a124942bacb8) cpu.hh (2669:f2b336e89d2a)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 10 unchanged lines hidden (view full) ---

19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 10 unchanged lines hidden (view full) ---

19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
27 */
28
31//Todo: Add in a lot of the functions that are ISA specific. Also define
32//the functions that currently exist within the base cpu class. Define
33//everything for the simobject stuff so it can be serialized and
34//instantiated, add in debugging statements everywhere. Have CPU schedule
35//itself properly. Threads!
36// Avoid running stages and advancing queues if idle/stalled.
29#ifndef __CPU_O3_CPU_HH__
30#define __CPU_O3_CPU_HH__
37
31
38#ifndef __CPU_O3_CPU_FULL_CPU_HH__
39#define __CPU_O3_CPU_FULL_CPU_HH__
40
41#include <iostream>
42#include <list>
32#include <iostream>
33#include <list>
34#include <queue>
35#include <set>
43#include <vector>
44
36#include <vector>
37
38#include "arch/isa_traits.hh"
45#include "base/statistics.hh"
46#include "base/timebuf.hh"
47#include "config/full_system.hh"
39#include "base/statistics.hh"
40#include "base/timebuf.hh"
41#include "config/full_system.hh"
42#include "cpu/activity.hh"
48#include "cpu/base.hh"
49#include "cpu/cpu_exec_context.hh"
50#include "cpu/o3/comm.hh"
51#include "cpu/o3/cpu_policy.hh"
43#include "cpu/base.hh"
44#include "cpu/cpu_exec_context.hh"
45#include "cpu/o3/comm.hh"
46#include "cpu/o3/cpu_policy.hh"
47#include "cpu/o3/scoreboard.hh"
48#include "cpu/o3/thread_state.hh"
52#include "sim/process.hh"
53
49#include "sim/process.hh"
50
51template <class>
52class Checker;
54class ExecContext;
53class ExecContext;
55class FunctionalMemory;
54class MemObject;
56class Process;
57
58class BaseFullCPU : public BaseCPU
59{
60 //Stuff that's pretty ISA independent will go here.
61 public:
62 typedef BaseCPU::Params Params;
63
55class Process;
56
57class BaseFullCPU : public BaseCPU
58{
59 //Stuff that's pretty ISA independent will go here.
60 public:
61 typedef BaseCPU::Params Params;
62
64#if FULL_SYSTEM
65 BaseFullCPU(Params &params);
66#else
67 BaseFullCPU(Params &params);
68#endif // FULL_SYSTEM
63 BaseFullCPU(Params *params);
69
64
65 void regStats();
66
67 int readCpuId() { return cpu_id; }
68
70 protected:
71 int cpu_id;
72};
73
74template <class Impl>
75class FullO3CPU : public BaseFullCPU
76{
77 public:
69 protected:
70 int cpu_id;
71};
72
73template <class Impl>
74class FullO3CPU : public BaseFullCPU
75{
76 public:
78 //Put typedefs from the Impl here.
77 typedef TheISA::FloatReg FloatReg;
78 typedef TheISA::FloatRegBits FloatRegBits;
79
80 // Typedefs from the Impl here.
79 typedef typename Impl::CPUPol CPUPolicy;
80 typedef typename Impl::Params Params;
81 typedef typename Impl::DynInstPtr DynInstPtr;
82
81 typedef typename Impl::CPUPol CPUPolicy;
82 typedef typename Impl::Params Params;
83 typedef typename Impl::DynInstPtr DynInstPtr;
84
85 typedef O3ThreadState<Impl> Thread;
86
87 typedef typename std::list<DynInstPtr>::iterator ListIt;
88
83 public:
84 enum Status {
85 Running,
86 Idle,
87 Halted,
89 public:
90 enum Status {
91 Running,
92 Idle,
93 Halted,
88 Blocked // ?
94 Blocked,
95 SwitchedOut
89 };
90
96 };
97
98 /** Overall CPU status. */
91 Status _status;
92
93 private:
94 class TickEvent : public Event
95 {
96 private:
99 Status _status;
100
101 private:
102 class TickEvent : public Event
103 {
104 private:
105 /** Pointer to the CPU. */
97 FullO3CPU<Impl> *cpu;
98
99 public:
106 FullO3CPU<Impl> *cpu;
107
108 public:
109 /** Constructs a tick event. */
100 TickEvent(FullO3CPU<Impl> *c);
110 TickEvent(FullO3CPU<Impl> *c);
111
112 /** Processes a tick event, calling tick() on the CPU. */
101 void process();
113 void process();
114 /** Returns the description of the tick event. */
102 const char *description();
103 };
104
115 const char *description();
116 };
117
118 /** The tick event used for scheduling CPU ticks. */
105 TickEvent tickEvent;
106
119 TickEvent tickEvent;
120
107 /// Schedule tick event, regardless of its current state.
121 /** Schedule tick event, regardless of its current state. */
108 void scheduleTickEvent(int delay)
109 {
110 if (tickEvent.squashed())
122 void scheduleTickEvent(int delay)
123 {
124 if (tickEvent.squashed())
111 tickEvent.reschedule(curTick + delay);
125 tickEvent.reschedule(curTick + cycles(delay));
112 else if (!tickEvent.scheduled())
126 else if (!tickEvent.scheduled())
113 tickEvent.schedule(curTick + delay);
127 tickEvent.schedule(curTick + cycles(delay));
114 }
115
128 }
129
116 /// Unschedule tick event, regardless of its current state.
130 /** Unschedule tick event, regardless of its current state. */
117 void unscheduleTickEvent()
118 {
119 if (tickEvent.scheduled())
120 tickEvent.squash();
121 }
122
123 public:
131 void unscheduleTickEvent()
132 {
133 if (tickEvent.scheduled())
134 tickEvent.squash();
135 }
136
137 public:
124 FullO3CPU(Params &params);
138 /** Constructs a CPU with the given parameters. */
139 FullO3CPU(Params *params);
140 /** Destructor. */
125 ~FullO3CPU();
126
141 ~FullO3CPU();
142
143 /** Registers statistics. */
127 void fullCPURegStats();
128
144 void fullCPURegStats();
145
146 /** Ticks CPU, calling tick() on each stage, and checking the overall
147 * activity to see if the CPU should deschedule itself.
148 */
129 void tick();
130
149 void tick();
150
151 /** Initialize the CPU */
131 void init();
132
152 void init();
153
133 void activateContext(int thread_num, int delay);
134 void suspendContext(int thread_num);
135 void deallocateContext(int thread_num);
136 void haltContext(int thread_num);
154 /** Setup CPU to insert a thread's context */
155 void insertThread(unsigned tid);
137
156
138 void switchOut();
157 /** Remove all of a thread's context from CPU */
158 void removeThread(unsigned tid);
159
160 /** Count the Total Instructions Committed in the CPU. */
161 virtual Counter totalInstructions() const
162 {
163 Counter total(0);
164
165 for (int i=0; i < thread.size(); i++)
166 total += thread[i]->numInst;
167
168 return total;
169 }
170
171 /** Add Thread to Active Threads List. */
172 void activateContext(int tid, int delay);
173
174 /** Remove Thread from Active Threads List */
175 void suspendContext(int tid);
176
177 /** Remove Thread from Active Threads List &&
178 * Remove Thread Context from CPU.
179 */
180 void deallocateContext(int tid);
181
182 /** Remove Thread from Active Threads List &&
183 * Remove Thread Context from CPU.
184 */
185 void haltContext(int tid);
186
187 /** Activate a Thread When CPU Resources are Available. */
188 void activateWhenReady(int tid);
189
190 /** Add or Remove a Thread Context in the CPU. */
191 void doContextSwitch();
192
193 /** Update The Order In Which We Process Threads. */
194 void updateThreadPriority();
195
196 /** Executes a syscall on this cycle.
197 * ---------------------------------------
198 * Note: this is a virtual function. CPU-Specific
199 * functionality defined in derived classes
200 */
201 virtual void syscall(int tid) { panic("Unimplemented!"); }
202
203 /** Check if there are any system calls pending. */
204 void checkSyscalls();
205
206 /** Switches out this CPU.
207 */
208 void switchOut(Sampler *sampler);
209
210 void signalSwitched();
211
212 /** Takes over from another CPU.
213 */
139 void takeOverFrom(BaseCPU *oldCPU);
140
141 /** Get the current instruction sequence number, and increment it. */
214 void takeOverFrom(BaseCPU *oldCPU);
215
216 /** Get the current instruction sequence number, and increment it. */
142 InstSeqNum getAndIncrementInstSeq();
217 InstSeqNum getAndIncrementInstSeq()
218 { return globalSeqNum++; }
143
144#if FULL_SYSTEM
145 /** Check if this address is a valid instruction address. */
146 bool validInstAddr(Addr addr) { return true; }
147
148 /** Check if this address is a valid data address. */
149 bool validDataAddr(Addr addr) { return true; }
150
151 /** Get instruction asid. */
219
220#if FULL_SYSTEM
221 /** Check if this address is a valid instruction address. */
222 bool validInstAddr(Addr addr) { return true; }
223
224 /** Check if this address is a valid data address. */
225 bool validDataAddr(Addr addr) { return true; }
226
227 /** Get instruction asid. */
152 int getInstAsid()
153 { return regFile.miscRegs.getInstAsid(); }
228 int getInstAsid(unsigned tid)
229 { return regFile.miscRegs[tid].getInstAsid(); }
154
155 /** Get data asid. */
230
231 /** Get data asid. */
156 int getDataAsid()
157 { return regFile.miscRegs.getDataAsid(); }
232 int getDataAsid(unsigned tid)
233 { return regFile.miscRegs[tid].getDataAsid(); }
158#else
234#else
159 bool validInstAddr(Addr addr)
160 { return thread[0]->validInstAddr(addr); }
235 /** Get instruction asid. */
236 int getInstAsid(unsigned tid)
237 { return thread[tid]->asid; }
161
238
162 bool validDataAddr(Addr addr)
163 { return thread[0]->validDataAddr(addr); }
239 /** Get data asid. */
240 int getDataAsid(unsigned tid)
241 { return thread[tid]->asid; }
164
242
165 int getInstAsid() { return thread[0]->getInstAsid(); }
166 int getDataAsid() { return thread[0]->getDataAsid(); }
167
168#endif
169
170 //
171 // New accessors for new decoder.
172 //
173 uint64_t readIntReg(int reg_idx);
174
175 FloatReg readFloatReg(int reg_idx);
176
177 FloatReg readFloatReg(int reg_idx, int width);
178
179 FloatRegBits readFloatRegBits(int reg_idx);
180
181 FloatRegBits readFloatRegBits(int reg_idx, int width);
182
183 void setIntReg(int reg_idx, uint64_t val);
184
243#endif
244
245 //
246 // New accessors for new decoder.
247 //
248 uint64_t readIntReg(int reg_idx);
249
250 FloatReg readFloatReg(int reg_idx);
251
252 FloatReg readFloatReg(int reg_idx, int width);
253
254 FloatRegBits readFloatRegBits(int reg_idx);
255
256 FloatRegBits readFloatRegBits(int reg_idx, int width);
257
258 void setIntReg(int reg_idx, uint64_t val);
259
185 void setFloatReg(int reg_idx, FloatReg val, int width);
260 void setFloatReg(int reg_idx, FloatReg val);
186
187 void setFloatReg(int reg_idx, FloatReg val, int width);
188
189 void setFloatRegBits(int reg_idx, FloatRegBits val);
190
261
262 void setFloatReg(int reg_idx, FloatReg val, int width);
263
264 void setFloatRegBits(int reg_idx, FloatRegBits val);
265
191 void setFloatRegBits(int reg_idx, FloatRegBits val);
266 void setFloatRegBits(int reg_idx, FloatRegBits val, int width);
192
267
193 uint64_t readPC();
268 uint64_t readArchIntReg(int reg_idx, unsigned tid);
194
269
195 void setNextPC(uint64_t val);
270 float readArchFloatRegSingle(int reg_idx, unsigned tid);
196
271
197 void setPC(Addr new_PC);
272 double readArchFloatRegDouble(int reg_idx, unsigned tid);
198
273
274 uint64_t readArchFloatRegInt(int reg_idx, unsigned tid);
275
276 void setArchIntReg(int reg_idx, uint64_t val, unsigned tid);
277
278 void setArchFloatRegSingle(int reg_idx, float val, unsigned tid);
279
280 void setArchFloatRegDouble(int reg_idx, double val, unsigned tid);
281
282 void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid);
283
284 uint64_t readPC(unsigned tid);
285
286 void setPC(Addr new_PC,unsigned tid);
287
288 uint64_t readNextPC(unsigned tid);
289
290 void setNextPC(uint64_t val,unsigned tid);
291
199 /** Function to add instruction onto the head of the list of the
200 * instructions. Used when new instructions are fetched.
201 */
292 /** Function to add instruction onto the head of the list of the
293 * instructions. Used when new instructions are fetched.
294 */
202 void addInst(DynInstPtr &inst);
295 ListIt addInst(DynInstPtr &inst);
203
204 /** Function to tell the CPU that an instruction has completed. */
296
297 /** Function to tell the CPU that an instruction has completed. */
205 void instDone();
298 void instDone(unsigned tid);
206
299
207 /** Remove all instructions in back of the given instruction, but leave
208 * that instruction in the list. This is useful in a squash, when there
209 * are instructions in this list that don't exist in structures such as
210 * the ROB. The instruction doesn't have to be the last instruction in
211 * the list, but will be once this function completes.
212 * @todo: Remove only up until that inst? Squashed inst is most likely
213 * valid.
214 */
215 void removeBackInst(DynInstPtr &inst);
300 /** Add Instructions to the CPU Remove List*/
301 void addToRemoveList(DynInstPtr &inst);
216
302
217 /** Remove an instruction from the front of the list. It is expected
218 * that there are no instructions in front of it (that is, none are older
219 * than the instruction being removed). Used when retiring instructions.
220 * @todo: Remove the argument to this function, and just have it remove
221 * last instruction once it's verified that commit has the same ordering
222 * as the instruction list.
303 /** Remove an instruction from the front end of the list. There's
304 * no restriction on location of the instruction.
223 */
224 void removeFrontInst(DynInstPtr &inst);
225
226 /** Remove all instructions that are not currently in the ROB. */
305 */
306 void removeFrontInst(DynInstPtr &inst);
307
308 /** Remove all instructions that are not currently in the ROB. */
227 void removeInstsNotInROB();
309 void removeInstsNotInROB(unsigned tid);
228
229 /** Remove all instructions younger than the given sequence number. */
310
311 /** Remove all instructions younger than the given sequence number. */
230 void removeInstsUntil(const InstSeqNum &seq_num);
312 void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
231
313
314 inline void squashInstIt(const ListIt &instIt, const unsigned &tid);
315
316 void cleanUpRemovedInsts();
317
232 /** Remove all instructions from the list. */
318 /** Remove all instructions from the list. */
233 void removeAllInsts();
319// void removeAllInsts();
234
235 void dumpInsts();
236
237 /** Basically a wrapper function so that instructions executed at
320
321 void dumpInsts();
322
323 /** Basically a wrapper function so that instructions executed at
238 * commit can tell the instruction queue that they have completed.
239 * Eventually this hack should be removed.
324 * commit can tell the instruction queue that they have
325 * completed. Eventually this hack should be removed.
240 */
326 */
241 void wakeDependents(DynInstPtr &inst);
327// void wakeDependents(DynInstPtr &inst);
242
243 public:
244 /** List of all the instructions in flight. */
328
329 public:
330 /** List of all the instructions in flight. */
245 list instList;
331 std::list<DynInstPtr> instList;
246
332
247 //not sure these should be private.
333 /** List of all the instructions that will be removed at the end of this
334 * cycle.
335 */
336 std::queue<ListIt> removeList;
337
338#ifdef DEBUG
339 std::set<InstSeqNum> snList;
340#endif
341
342 /** Records if instructions need to be removed this cycle due to
343 * being retired or squashed.
344 */
345 bool removeInstsThisCycle;
346
248 protected:
249 /** The fetch stage. */
250 typename CPUPolicy::Fetch fetch;
251
347 protected:
348 /** The fetch stage. */
349 typename CPUPolicy::Fetch fetch;
350
252 /** The fetch stage's status. */
253 typename CPUPolicy::Fetch::Status fetchStatus;
254
255 /** The decode stage. */
256 typename CPUPolicy::Decode decode;
257
351 /** The decode stage. */
352 typename CPUPolicy::Decode decode;
353
258 /** The decode stage's status. */
259 typename CPUPolicy::Decode::Status decodeStatus;
260
261 /** The dispatch stage. */
262 typename CPUPolicy::Rename rename;
263
354 /** The dispatch stage. */
355 typename CPUPolicy::Rename rename;
356
264 /** The dispatch stage's status. */
265 typename CPUPolicy::Rename::Status renameStatus;
266
267 /** The issue/execute/writeback stages. */
268 typename CPUPolicy::IEW iew;
269
357 /** The issue/execute/writeback stages. */
358 typename CPUPolicy::IEW iew;
359
270 /** The issue/execute/writeback stage's status. */
271 typename CPUPolicy::IEW::Status iewStatus;
272
273 /** The commit stage. */
274 typename CPUPolicy::Commit commit;
275
360 /** The commit stage. */
361 typename CPUPolicy::Commit commit;
362
276 /** The fetch stage's status. */
277 typename CPUPolicy::Commit::Status commitStatus;
278
279 //Might want to just pass these objects in to the constructors of the
280 //appropriate stage. regFile is in iew, freeList in dispatch, renameMap
281 //in dispatch, and the rob in commit.
282 /** The register file. */
283 typename CPUPolicy::RegFile regFile;
284
285 /** The free list. */
286 typename CPUPolicy::FreeList freeList;
287
288 /** The rename map. */
363 /** The register file. */
364 typename CPUPolicy::RegFile regFile;
365
366 /** The free list. */
367 typename CPUPolicy::FreeList freeList;
368
369 /** The rename map. */
289 typename CPUPolicy::RenameMap renameMap;
370 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
290
371
372 /** The commit rename map. */
373 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
374
291 /** The re-order buffer. */
292 typename CPUPolicy::ROB rob;
293
375 /** The re-order buffer. */
376 typename CPUPolicy::ROB rob;
377
378 /** Active Threads List */
379 std::list<unsigned> activeThreads;
380
381 /** Integer Register Scoreboard */
382 Scoreboard scoreboard;
383
294 public:
384 public:
385 /** Enum to give each stage a specific index, so when calling
386 * activateStage() or deactivateStage(), they can specify which stage
387 * is being activated/deactivated.
388 */
389 enum StageIdx {
390 FetchIdx,
391 DecodeIdx,
392 RenameIdx,
393 IEWIdx,
394 CommitIdx,
395 NumStages };
396
295 /** Typedefs from the Impl to get the structs that each of the
296 * time buffers should use.
297 */
298 typedef typename CPUPolicy::TimeStruct TimeStruct;
299
300 typedef typename CPUPolicy::FetchStruct FetchStruct;
301
302 typedef typename CPUPolicy::DecodeStruct DecodeStruct;

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316
317 /** The rename stage's instruction queue. */
318 TimeBuffer<RenameStruct> renameQueue;
319
320 /** The IEW stage's instruction queue. */
321 TimeBuffer<IEWStruct> iewQueue;
322
323 public:
397 /** Typedefs from the Impl to get the structs that each of the
398 * time buffers should use.
399 */
400 typedef typename CPUPolicy::TimeStruct TimeStruct;
401
402 typedef typename CPUPolicy::FetchStruct FetchStruct;
403
404 typedef typename CPUPolicy::DecodeStruct DecodeStruct;

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418
419 /** The rename stage's instruction queue. */
420 TimeBuffer<RenameStruct> renameQueue;
421
422 /** The IEW stage's instruction queue. */
423 TimeBuffer<IEWStruct> iewQueue;
424
425 public:
324 /** The temporary exec context to support older accessors. */
325 CPUExecContext *cpuXC;
426 ActivityRecorder activityRec;
326
427
428 void activityThisCycle() { activityRec.activity(); }
429
430 void activateStage(const StageIdx idx)
431 { activityRec.activateStage(idx); }
432
433 void deactivateStage(const StageIdx idx)
434 { activityRec.deactivateStage(idx); }
435
436 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
437 void wakeCPU();
438
439 /** Gets a free thread id. Use if thread ids change across system. */
440 int getFreeTid();
441
442 public:
327 /** Temporary function to get pointer to exec context. */
443 /** Temporary function to get pointer to exec context. */
328 ExecContext *xcBase()
444 ExecContext *xcBase(unsigned tid)
329 {
445 {
330 return thread[0]->getProxy();
446 return thread[tid]->getXCProxy();
331 }
332
447 }
448
333 CPUExecContext *cpuXCBase()
334 {
335 return thread[0];
336 }
337
449 /** The global sequence number counter. */
338 InstSeqNum globalSeqNum;
339
450 InstSeqNum globalSeqNum;
451
452 Checker<DynInstPtr> *checker;
453
340#if FULL_SYSTEM
454#if FULL_SYSTEM
455 /** Pointer to the system. */
341 System *system;
342
456 System *system;
457
458 /** Pointer to the memory controller. */
343 MemoryController *memCtrl;
459 MemoryController *memCtrl;
460 /** Pointer to physical memory. */
344 PhysicalMemory *physmem;
461 PhysicalMemory *physmem;
462#endif
345
463
346 AlphaITB *itb;
347 AlphaDTB *dtb;
464 /** Pointer to memory. */
465 MemObject *mem;
348
466
349// SWContext *swCtx;
350#endif
351 std::vector<CPUExecContext *> thread;
467 Sampler *sampler;
352
468
353 FunctionalMemory *mem;
469 int switchCount;
354
470
471 // List of all ExecContexts.
472 std::vector<Thread *> thread;
473
474#if 0
475 /** Page table pointer. */
476 PageTable *pTable;
477#endif
478
479 /** Pointer to the icache interface. */
355 MemInterface *icacheInterface;
480 MemInterface *icacheInterface;
481 /** Pointer to the dcache interface. */
356 MemInterface *dcacheInterface;
357
482 MemInterface *dcacheInterface;
483
484 /** Whether or not the CPU should defer its registration. */
358 bool deferRegistration;
359
485 bool deferRegistration;
486
360 Counter numInsts;
487 /** Is there a context switch pending? */
488 bool contextSwitch;
361
489
362 Counter funcExeInst;
490 /** Threads Scheduled to Enter CPU */
491 std::list<int> cpuWaitList;
492
493 /** The cycle that the CPU was last running, used for statistics. */
494 Tick lastRunningCycle;
495
496 /** Number of Threads CPU can process */
497 unsigned numThreads;
498
499 /** Mapping for system thread id to cpu id */
500 std::map<unsigned,unsigned> threadMap;
501
502 /** Available thread ids in the cpu*/
503 std::vector<unsigned> tids;
504
505 /** Stat for total number of times the CPU is descheduled. */
506 Stats::Scalar<> timesIdled;
507 /** Stat for total number of cycles the CPU spends descheduled. */
508 Stats::Scalar<> idleCycles;
509 /** Stat for the number of committed instructions per thread. */
510 Stats::Vector<> committedInsts;
511 /** Stat for the total number of committed instructions. */
512 Stats::Scalar<> totalCommittedInsts;
513 /** Stat for the CPI per thread. */
514 Stats::Formula cpi;
515 /** Stat for the total CPI. */
516 Stats::Formula totalCpi;
517 /** Stat for the IPC per thread. */
518 Stats::Formula ipc;
519 /** Stat for the total IPC. */
520 Stats::Formula totalIpc;
363};
364
521};
522
365#endif
523#endif // __CPU_O3_CPU_HH__