cpu.hh (14194:967b9c450b04) cpu.hh (14195:c5efdb3319aa)
1/*
2 * Copyright (c) 2011-2013, 2016-2019 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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128 BaseTLB *dtb;
129 using LSQRequest = typename LSQ<Impl>::LSQRequest;
130
131 /** Overall CPU status. */
132 Status _status;
133
134 private:
135
1/*
2 * Copyright (c) 2011-2013, 2016-2019 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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128 BaseTLB *dtb;
129 using LSQRequest = typename LSQ<Impl>::LSQRequest;
130
131 /** Overall CPU status. */
132 Status _status;
133
134 private:
135
136 /**
137 * IcachePort class for instruction fetch.
138 */
139 class IcachePort : public MasterPort
140 {
141 protected:
142 /** Pointer to fetch. */
143 DefaultFetch<Impl> *fetch;
144
145 public:
146 /** Default constructor. */
147 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
148 : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
149 { }
150
151 protected:
152
153 /** Timing version of receive. Handles setting fetch to the
154 * proper status to start fetching. */
155 virtual bool recvTimingResp(PacketPtr pkt);
156
157 /** Handles doing a retry of a failed fetch. */
158 virtual void recvReqRetry();
159 };
160
161 /** The tick event used for scheduling CPU ticks. */
162 EventFunctionWrapper tickEvent;
163
164 /** The exit event used for terminating all ready-to-exit threads */
165 EventFunctionWrapper threadExitEvent;
166
167 /** Schedule tick event, regardless of its current state. */
168 void scheduleTickEvent(Cycles delay)

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624 */
625 std::unordered_map<ThreadID, bool> exitingThreads;
626
627 /** Integer Register Scoreboard */
628 Scoreboard scoreboard;
629
630 std::vector<TheISA::ISA *> isa;
631
136 /** The tick event used for scheduling CPU ticks. */
137 EventFunctionWrapper tickEvent;
138
139 /** The exit event used for terminating all ready-to-exit threads */
140 EventFunctionWrapper threadExitEvent;
141
142 /** Schedule tick event, regardless of its current state. */
143 void scheduleTickEvent(Cycles delay)

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599 */
600 std::unordered_map<ThreadID, bool> exitingThreads;
601
602 /** Integer Register Scoreboard */
603 Scoreboard scoreboard;
604
605 std::vector<TheISA::ISA *> isa;
606
632 /** Instruction port. Note that it has to appear after the fetch stage. */
633 IcachePort icachePort;
634
635 public:
636 /** Enum to give each stage a specific index, so when calling
637 * activateStage() or deactivateStage(), they can specify which stage
638 * is being activated/deactivated.
639 */
640 enum StageIdx {
641 FetchIdx,
642 DecodeIdx,

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758
759 /** CPU write function, forwards write to LSQ. */
760 Fault write(LSQRequest* req, uint8_t *data, int store_idx)
761 {
762 return this->iew.ldstQueue.write(req, data, store_idx);
763 }
764
765 /** Used by the fetch unit to get a hold of the instruction port. */
607 public:
608 /** Enum to give each stage a specific index, so when calling
609 * activateStage() or deactivateStage(), they can specify which stage
610 * is being activated/deactivated.
611 */
612 enum StageIdx {
613 FetchIdx,
614 DecodeIdx,

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730
731 /** CPU write function, forwards write to LSQ. */
732 Fault write(LSQRequest* req, uint8_t *data, int store_idx)
733 {
734 return this->iew.ldstQueue.write(req, data, store_idx);
735 }
736
737 /** Used by the fetch unit to get a hold of the instruction port. */
766 MasterPort &getInstPort() override { return icachePort; }
738 MasterPort &
739 getInstPort() override
740 {
741 return this->fetch.getInstPort();
742 }
767
768 /** Get the dcache port (used to find block size for translations). */
769 MasterPort &
770 getDataPort() override
771 {
772 return this->iew.ldstQueue.getDataPort();
773 }
774

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744 /** Get the dcache port (used to find block size for translations). */
745 MasterPort &
746 getDataPort() override
747 {
748 return this->iew.ldstQueue.getDataPort();
749 }
750

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