| cpu.hh (13611:c8b7847b4171) | cpu.hh (13622:ba31c2a23eca) |
|---|---|
| 1/* 2 * Copyright (c) 2011-2013, 2016-2019 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 449 unchanged lines hidden (view full) --- 458 } 459 460 const VecElem& readVecElem(PhysRegIdPtr reg_idx) const; 461 462 const VecPredRegContainer& readVecPredReg(PhysRegIdPtr reg_idx) const; 463 464 VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr reg_idx); 465 | 1/* 2 * Copyright (c) 2011-2013, 2016-2019 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 449 unchanged lines hidden (view full) --- 458 } 459 460 const VecElem& readVecElem(PhysRegIdPtr reg_idx) const; 461 462 const VecPredRegContainer& readVecPredReg(PhysRegIdPtr reg_idx) const; 463 464 VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr reg_idx); 465 |
| 466 TheISA::CCReg readCCReg(PhysRegIdPtr phys_reg); | 466 RegVal readCCReg(PhysRegIdPtr phys_reg); |
| 467 468 void setIntReg(PhysRegIdPtr phys_reg, RegVal val); 469 470 void setFloatReg(PhysRegIdPtr phys_reg, RegVal val); 471 472 void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val); 473 474 void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val); 475 476 void setVecPredReg(PhysRegIdPtr reg_idx, const VecPredRegContainer& val); 477 | 467 468 void setIntReg(PhysRegIdPtr phys_reg, RegVal val); 469 470 void setFloatReg(PhysRegIdPtr phys_reg, RegVal val); 471 472 void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val); 473 474 void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val); 475 476 void setVecPredReg(PhysRegIdPtr reg_idx, const VecPredRegContainer& val); 477 |
| 478 void setCCReg(PhysRegIdPtr phys_reg, TheISA::CCReg val); | 478 void setCCReg(PhysRegIdPtr phys_reg, RegVal val); |
| 479 480 RegVal readArchIntReg(int reg_idx, ThreadID tid); 481 482 RegVal readArchFloatReg(int reg_idx, ThreadID tid); 483 484 const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const; 485 /** Read architectural vector register for modification. */ 486 VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID tid); --- 22 unchanged lines hidden (view full) --- 509 const VecElem& readArchVecElem(const RegIndex& reg_idx, 510 const ElemIndex& ldx, ThreadID tid) const; 511 512 const VecPredRegContainer& readArchVecPredReg(int reg_idx, 513 ThreadID tid) const; 514 515 VecPredRegContainer& getWritableArchVecPredReg(int reg_idx, ThreadID tid); 516 | 479 480 RegVal readArchIntReg(int reg_idx, ThreadID tid); 481 482 RegVal readArchFloatReg(int reg_idx, ThreadID tid); 483 484 const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const; 485 /** Read architectural vector register for modification. */ 486 VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID tid); --- 22 unchanged lines hidden (view full) --- 509 const VecElem& readArchVecElem(const RegIndex& reg_idx, 510 const ElemIndex& ldx, ThreadID tid) const; 511 512 const VecPredRegContainer& readArchVecPredReg(int reg_idx, 513 ThreadID tid) const; 514 515 VecPredRegContainer& getWritableArchVecPredReg(int reg_idx, ThreadID tid); 516 |
| 517 TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid); | 517 RegVal readArchCCReg(int reg_idx, ThreadID tid); |
| 518 519 /** Architectural register accessors. Looks up in the commit 520 * rename table to obtain the true physical index of the 521 * architected register first, then accesses that physical 522 * register. 523 */ 524 void setArchIntReg(int reg_idx, RegVal val, ThreadID tid); 525 526 void setArchFloatReg(int reg_idx, RegVal val, ThreadID tid); 527 528 void setArchVecPredReg(int reg_idx, const VecPredRegContainer& val, 529 ThreadID tid); 530 531 void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid); 532 533 void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, 534 const VecElem& val, ThreadID tid); 535 | 518 519 /** Architectural register accessors. Looks up in the commit 520 * rename table to obtain the true physical index of the 521 * architected register first, then accesses that physical 522 * register. 523 */ 524 void setArchIntReg(int reg_idx, RegVal val, ThreadID tid); 525 526 void setArchFloatReg(int reg_idx, RegVal val, ThreadID tid); 527 528 void setArchVecPredReg(int reg_idx, const VecPredRegContainer& val, 529 ThreadID tid); 530 531 void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid); 532 533 void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, 534 const VecElem& val, ThreadID tid); 535 |
| 536 void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid); | 536 void setArchCCReg(int reg_idx, RegVal val, ThreadID tid); |
| 537 538 /** Sets the commit PC state of a specific thread. */ 539 void pcState(const TheISA::PCState &newPCState, ThreadID tid); 540 541 /** Reads the commit PC state of a specific thread. */ 542 TheISA::PCState pcState(ThreadID tid); 543 544 /** Reads the commit PC of a specific thread. */ --- 291 unchanged lines hidden --- | 537 538 /** Sets the commit PC state of a specific thread. */ 539 void pcState(const TheISA::PCState &newPCState, ThreadID tid); 540 541 /** Reads the commit PC state of a specific thread. */ 542 TheISA::PCState pcState(ThreadID tid); 543 544 /** Reads the commit PC of a specific thread. */ --- 291 unchanged lines hidden --- |