cpu.hh (13601:f5c84915eb7f) | cpu.hh (13610:5d5404ac6288) |
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1/* 2 * Copyright (c) 2011-2013, 2016-2019 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 93 unchanged lines hidden (view full) --- 102 // Typedefs from the Impl here. 103 typedef typename Impl::CPUPol CPUPolicy; 104 typedef typename Impl::DynInstPtr DynInstPtr; 105 typedef typename Impl::O3CPU O3CPU; 106 107 using VecElem = TheISA::VecElem; 108 using VecRegContainer = TheISA::VecRegContainer; 109 | 1/* 2 * Copyright (c) 2011-2013, 2016-2019 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 93 unchanged lines hidden (view full) --- 102 // Typedefs from the Impl here. 103 typedef typename Impl::CPUPol CPUPolicy; 104 typedef typename Impl::DynInstPtr DynInstPtr; 105 typedef typename Impl::O3CPU O3CPU; 106 107 using VecElem = TheISA::VecElem; 108 using VecRegContainer = TheISA::VecRegContainer; 109 |
110 using VecPredRegContainer = TheISA::VecPredRegContainer; 111 |
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110 typedef O3ThreadState<Impl> ImplState; 111 typedef O3ThreadState<Impl> Thread; 112 113 typedef typename std::list<DynInstPtr>::iterator ListIt; 114 115 friend class O3ThreadContext<Impl>; 116 117 public: --- 334 unchanged lines hidden (view full) --- 452 setVecLane(PhysRegIdPtr phys_reg, const LD& val) 453 { 454 vecRegfileWrites++; 455 return regFile.setVecLane(phys_reg, val); 456 } 457 458 const VecElem& readVecElem(PhysRegIdPtr reg_idx) const; 459 | 112 typedef O3ThreadState<Impl> ImplState; 113 typedef O3ThreadState<Impl> Thread; 114 115 typedef typename std::list<DynInstPtr>::iterator ListIt; 116 117 friend class O3ThreadContext<Impl>; 118 119 public: --- 334 unchanged lines hidden (view full) --- 454 setVecLane(PhysRegIdPtr phys_reg, const LD& val) 455 { 456 vecRegfileWrites++; 457 return regFile.setVecLane(phys_reg, val); 458 } 459 460 const VecElem& readVecElem(PhysRegIdPtr reg_idx) const; 461 |
462 const VecPredRegContainer& readVecPredReg(PhysRegIdPtr reg_idx) const; 463 464 VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr reg_idx); 465 |
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460 TheISA::CCReg readCCReg(PhysRegIdPtr phys_reg); 461 462 void setIntReg(PhysRegIdPtr phys_reg, RegVal val); 463 464 void setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val); 465 466 void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val); 467 468 void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val); 469 | 466 TheISA::CCReg readCCReg(PhysRegIdPtr phys_reg); 467 468 void setIntReg(PhysRegIdPtr phys_reg, RegVal val); 469 470 void setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val); 471 472 void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val); 473 474 void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val); 475 |
476 void setVecPredReg(PhysRegIdPtr reg_idx, const VecPredRegContainer& val); 477 |
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470 void setCCReg(PhysRegIdPtr phys_reg, TheISA::CCReg val); 471 472 RegVal readArchIntReg(int reg_idx, ThreadID tid); 473 474 RegVal readArchFloatRegBits(int reg_idx, ThreadID tid); 475 476 const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const; 477 /** Read architectural vector register for modification. */ --- 18 unchanged lines hidden (view full) --- 496 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 497 RegId(VecRegClass, reg_idx)); 498 setVecLane(phys_reg, val); 499 } 500 501 const VecElem& readArchVecElem(const RegIndex& reg_idx, 502 const ElemIndex& ldx, ThreadID tid) const; 503 | 478 void setCCReg(PhysRegIdPtr phys_reg, TheISA::CCReg val); 479 480 RegVal readArchIntReg(int reg_idx, ThreadID tid); 481 482 RegVal readArchFloatRegBits(int reg_idx, ThreadID tid); 483 484 const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const; 485 /** Read architectural vector register for modification. */ --- 18 unchanged lines hidden (view full) --- 504 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 505 RegId(VecRegClass, reg_idx)); 506 setVecLane(phys_reg, val); 507 } 508 509 const VecElem& readArchVecElem(const RegIndex& reg_idx, 510 const ElemIndex& ldx, ThreadID tid) const; 511 |
512 const VecPredRegContainer& readArchVecPredReg(int reg_idx, 513 ThreadID tid) const; 514 515 VecPredRegContainer& getWritableArchVecPredReg(int reg_idx, ThreadID tid); 516 |
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504 TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid); 505 506 /** Architectural register accessors. Looks up in the commit 507 * rename table to obtain the true physical index of the 508 * architected register first, then accesses that physical 509 * register. 510 */ 511 void setArchIntReg(int reg_idx, RegVal val, ThreadID tid); 512 513 void setArchFloatRegBits(int reg_idx, RegVal val, ThreadID tid); 514 | 517 TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid); 518 519 /** Architectural register accessors. Looks up in the commit 520 * rename table to obtain the true physical index of the 521 * architected register first, then accesses that physical 522 * register. 523 */ 524 void setArchIntReg(int reg_idx, RegVal val, ThreadID tid); 525 526 void setArchFloatRegBits(int reg_idx, RegVal val, ThreadID tid); 527 |
528 void setArchVecPredReg(int reg_idx, const VecPredRegContainer& val, 529 ThreadID tid); 530 |
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515 void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid); 516 517 void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, 518 const VecElem& val, ThreadID tid); 519 520 void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid); 521 522 /** Sets the commit PC state of a specific thread. */ --- 277 unchanged lines hidden (view full) --- 800 Stats::Scalar intRegfileReads; 801 Stats::Scalar intRegfileWrites; 802 //number of float register file accesses 803 Stats::Scalar fpRegfileReads; 804 Stats::Scalar fpRegfileWrites; 805 //number of vector register file accesses 806 mutable Stats::Scalar vecRegfileReads; 807 Stats::Scalar vecRegfileWrites; | 531 void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid); 532 533 void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, 534 const VecElem& val, ThreadID tid); 535 536 void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid); 537 538 /** Sets the commit PC state of a specific thread. */ --- 277 unchanged lines hidden (view full) --- 816 Stats::Scalar intRegfileReads; 817 Stats::Scalar intRegfileWrites; 818 //number of float register file accesses 819 Stats::Scalar fpRegfileReads; 820 Stats::Scalar fpRegfileWrites; 821 //number of vector register file accesses 822 mutable Stats::Scalar vecRegfileReads; 823 Stats::Scalar vecRegfileWrites; |
824 //number of predicate register file accesses 825 mutable Stats::Scalar vecPredRegfileReads; 826 Stats::Scalar vecPredRegfileWrites; |
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808 //number of CC register file accesses 809 Stats::Scalar ccRegfileReads; 810 Stats::Scalar ccRegfileWrites; 811 //number of misc 812 Stats::Scalar miscRegfileReads; 813 Stats::Scalar miscRegfileWrites; 814}; 815 816#endif // __CPU_O3_CPU_HH__ | 827 //number of CC register file accesses 828 Stats::Scalar ccRegfileReads; 829 Stats::Scalar ccRegfileWrites; 830 //number of misc 831 Stats::Scalar miscRegfileReads; 832 Stats::Scalar miscRegfileWrites; 833}; 834 835#endif // __CPU_O3_CPU_HH__ |