cpu.hh (13582:989577bf6abc) cpu.hh (13590:d7e018859709)
1/*
1/*
2 * Copyright (c) 2011-2013, 2016 ARM Limited
2 * Copyright (c) 2011-2013, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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120 Idle,
121 Halted,
122 Blocked,
123 SwitchedOut
124 };
125
126 BaseTLB *itb;
127 BaseTLB *dtb;
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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120 Idle,
121 Halted,
122 Blocked,
123 SwitchedOut
124 };
125
126 BaseTLB *itb;
127 BaseTLB *dtb;
128 using LSQRequest = typename LSQ<Impl>::LSQRequest;
128
129 /** Overall CPU status. */
130 Status _status;
131
132 private:
133
134 /**
135 * IcachePort class for instruction fetch.

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728 Tick lastActivatedCycle;
729
730 /** Mapping for system thread id to cpu id */
731 std::map<ThreadID, unsigned> threadMap;
732
733 /** Available thread ids in the cpu*/
734 std::vector<ThreadID> tids;
735
129
130 /** Overall CPU status. */
131 Status _status;
132
133 private:
134
135 /**
136 * IcachePort class for instruction fetch.

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729 Tick lastActivatedCycle;
730
731 /** Mapping for system thread id to cpu id */
732 std::map<ThreadID, unsigned> threadMap;
733
734 /** Available thread ids in the cpu*/
735 std::vector<ThreadID> tids;
736
737 /** CPU pushRequest function, forwards request to LSQ. */
738 Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
739 unsigned int size, Addr addr, Request::Flags flags,
740 uint64_t *res)
741 {
742 return iew.ldstQueue.pushRequest(inst, isLoad, data, size, addr,
743 flags, res);
744 }
745
736 /** CPU read function, forwards read to LSQ. */
746 /** CPU read function, forwards read to LSQ. */
737 Fault read(const RequestPtr &req,
738 RequestPtr &sreqLow, RequestPtr &sreqHigh,
739 int load_idx)
747 Fault read(LSQRequest* req, int load_idx)
740 {
748 {
741 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, load_idx);
749 return this->iew.ldstQueue.read(req, load_idx);
742 }
743
744 /** CPU write function, forwards write to LSQ. */
750 }
751
752 /** CPU write function, forwards write to LSQ. */
745 Fault write(const RequestPtr &req,
746 const RequestPtr &sreqLow, const RequestPtr &sreqHigh,
747 uint8_t *data, int store_idx)
753 Fault write(LSQRequest* req, uint8_t *data, int store_idx)
748 {
754 {
749 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
750 data, store_idx);
755 return this->iew.ldstQueue.write(req, data, store_idx);
751 }
752
753 /** Used by the fetch unit to get a hold of the instruction port. */
754 MasterPort &getInstPort() override { return icachePort; }
755
756 /** Get the dcache port (used to find block size for translations). */
757 MasterPort &getDataPort() override { return dcachePort; }
758

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757
758 /** Used by the fetch unit to get a hold of the instruction port. */
759 MasterPort &getInstPort() override { return icachePort; }
760
761 /** Get the dcache port (used to find block size for translations). */
762 MasterPort &getDataPort() override { return dcachePort; }
763

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