cpu.hh (12105:742d80361989) cpu.hh (12109:f29e9c5418aa)
1/*
1/*
2 * Copyright (c) 2011-2013 ARM Limited
2 * Copyright (c) 2011-2013, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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48#define __CPU_O3_CPU_HH__
49
50#include <iostream>
51#include <list>
52#include <queue>
53#include <set>
54#include <vector>
55
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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48#define __CPU_O3_CPU_HH__
49
50#include <iostream>
51#include <list>
52#include <queue>
53#include <set>
54#include <vector>
55
56#include "arch/generic/types.hh"
56#include "arch/types.hh"
57#include "base/statistics.hh"
58#include "config/the_isa.hh"
59#include "cpu/o3/comm.hh"
60#include "cpu/o3/cpu_policy.hh"
61#include "cpu/o3/scoreboard.hh"
62#include "cpu/o3/thread_state.hh"
63#include "cpu/activity.hh"

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98class FullO3CPU : public BaseO3CPU
99{
100 public:
101 // Typedefs from the Impl here.
102 typedef typename Impl::CPUPol CPUPolicy;
103 typedef typename Impl::DynInstPtr DynInstPtr;
104 typedef typename Impl::O3CPU O3CPU;
105
57#include "arch/types.hh"
58#include "base/statistics.hh"
59#include "config/the_isa.hh"
60#include "cpu/o3/comm.hh"
61#include "cpu/o3/cpu_policy.hh"
62#include "cpu/o3/scoreboard.hh"
63#include "cpu/o3/thread_state.hh"
64#include "cpu/activity.hh"

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99class FullO3CPU : public BaseO3CPU
100{
101 public:
102 // Typedefs from the Impl here.
103 typedef typename Impl::CPUPol CPUPolicy;
104 typedef typename Impl::DynInstPtr DynInstPtr;
105 typedef typename Impl::O3CPU O3CPU;
106
107 using VecElem = TheISA::VecElem;
108 using VecRegContainer = TheISA::VecRegContainer;
109
106 typedef O3ThreadState<Impl> ImplState;
107 typedef O3ThreadState<Impl> Thread;
108
109 typedef typename std::list<DynInstPtr>::iterator ListIt;
110
111 friend class O3ThreadContext<Impl>;
112
113 public:

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412 ThreadID tid);
413
414 uint64_t readIntReg(PhysRegIdPtr phys_reg);
415
416 TheISA::FloatReg readFloatReg(PhysRegIdPtr phys_reg);
417
418 TheISA::FloatRegBits readFloatRegBits(PhysRegIdPtr phys_reg);
419
110 typedef O3ThreadState<Impl> ImplState;
111 typedef O3ThreadState<Impl> Thread;
112
113 typedef typename std::list<DynInstPtr>::iterator ListIt;
114
115 friend class O3ThreadContext<Impl>;
116
117 public:

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416 ThreadID tid);
417
418 uint64_t readIntReg(PhysRegIdPtr phys_reg);
419
420 TheISA::FloatReg readFloatReg(PhysRegIdPtr phys_reg);
421
422 TheISA::FloatRegBits readFloatRegBits(PhysRegIdPtr phys_reg);
423
424 const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const;
425
426 /**
427 * Read physical vector register for modification.
428 */
429 VecRegContainer& getWritableVecReg(PhysRegIdPtr reg_idx);
430
431 /**
432 * Read physical vector register lane
433 */
434 template<typename VecElem, int LaneIdx>
435 VecLaneT<VecElem, true>
436 readVecLane(PhysRegIdPtr phys_reg) const
437 {
438 vecRegfileReads++;
439 return regFile.readVecLane<VecElem, LaneIdx>(phys_reg);
440 }
441
442 /**
443 * Read physical vector register lane
444 */
445 template<typename VecElem>
446 VecLaneT<VecElem, true>
447 readVecLane(PhysRegIdPtr phys_reg) const
448 {
449 vecRegfileReads++;
450 return regFile.readVecLane<VecElem>(phys_reg);
451 }
452
453 /** Write a lane of the destination vector register. */
454 template<typename LD>
455 void
456 setVecLane(PhysRegIdPtr phys_reg, const LD& val)
457 {
458 vecRegfileWrites++;
459 return regFile.setVecLane(phys_reg, val);
460 }
461
462 const VecElem& readVecElem(PhysRegIdPtr reg_idx) const;
463
420 TheISA::CCReg readCCReg(PhysRegIdPtr phys_reg);
421
422 void setIntReg(PhysRegIdPtr phys_reg, uint64_t val);
423
424 void setFloatReg(PhysRegIdPtr phys_reg, TheISA::FloatReg val);
425
426 void setFloatRegBits(PhysRegIdPtr phys_reg, TheISA::FloatRegBits val);
427
464 TheISA::CCReg readCCReg(PhysRegIdPtr phys_reg);
465
466 void setIntReg(PhysRegIdPtr phys_reg, uint64_t val);
467
468 void setFloatReg(PhysRegIdPtr phys_reg, TheISA::FloatReg val);
469
470 void setFloatRegBits(PhysRegIdPtr phys_reg, TheISA::FloatRegBits val);
471
472 void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val);
473
474 void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val);
475
428 void setCCReg(PhysRegIdPtr phys_reg, TheISA::CCReg val);
429
430 uint64_t readArchIntReg(int reg_idx, ThreadID tid);
431
432 float readArchFloatReg(int reg_idx, ThreadID tid);
433
434 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
435
476 void setCCReg(PhysRegIdPtr phys_reg, TheISA::CCReg val);
477
478 uint64_t readArchIntReg(int reg_idx, ThreadID tid);
479
480 float readArchFloatReg(int reg_idx, ThreadID tid);
481
482 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
483
484 const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const;
485 /** Read architectural vector register for modification. */
486 VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID tid);
487
488 /** Read architectural vector register lane. */
489 template<typename VecElem>
490 VecLaneT<VecElem, true>
491 readArchVecLane(int reg_idx, int lId, ThreadID tid) const
492 {
493 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
494 RegId(VecRegClass, reg_idx));
495 return readVecLane<VecElem>(phys_reg);
496 }
497
498
499 /** Write a lane of the destination vector register. */
500 template<typename LD>
501 void
502 setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val)
503 {
504 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
505 RegId(VecRegClass, reg_idx));
506 setVecLane(phys_reg, val);
507 }
508
509 const VecElem& readArchVecElem(const RegIndex& reg_idx,
510 const ElemIndex& ldx, ThreadID tid) const;
511
436 TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid);
437
438 /** Architectural register accessors. Looks up in the commit
439 * rename table to obtain the true physical index of the
440 * architected register first, then accesses that physical
441 * register.
442 */
443 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
444
445 void setArchFloatReg(int reg_idx, float val, ThreadID tid);
446
447 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
448
512 TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid);
513
514 /** Architectural register accessors. Looks up in the commit
515 * rename table to obtain the true physical index of the
516 * architected register first, then accesses that physical
517 * register.
518 */
519 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
520
521 void setArchFloatReg(int reg_idx, float val, ThreadID tid);
522
523 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
524
525 void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid);
526
527 void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
528 const VecElem& val, ThreadID tid);
529
449 void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid);
450
451 /** Sets the commit PC state of a specific thread. */
452 void pcState(const TheISA::PCState &newPCState, ThreadID tid);
453
454 /** Reads the commit PC state of a specific thread. */
455 TheISA::PCState pcState(ThreadID tid);
456

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535 typename CPUPolicy::Rename rename;
536
537 /** The issue/execute/writeback stages. */
538 typename CPUPolicy::IEW iew;
539
540 /** The commit stage. */
541 typename CPUPolicy::Commit commit;
542
530 void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid);
531
532 /** Sets the commit PC state of a specific thread. */
533 void pcState(const TheISA::PCState &newPCState, ThreadID tid);
534
535 /** Reads the commit PC state of a specific thread. */
536 TheISA::PCState pcState(ThreadID tid);
537

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616 typename CPUPolicy::Rename rename;
617
618 /** The issue/execute/writeback stages. */
619 typename CPUPolicy::IEW iew;
620
621 /** The commit stage. */
622 typename CPUPolicy::Commit commit;
623
624 /** The rename mode of the vector registers */
625 Enums::VecRegRenameMode vecMode;
626
543 /** The register file. */
544 PhysRegFile regFile;
545
546 /** The free list. */
547 typename CPUPolicy::FreeList freeList;
548
549 /** The rename map. */
550 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];

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717 Stats::Formula totalIpc;
718
719 //number of integer register file accesses
720 Stats::Scalar intRegfileReads;
721 Stats::Scalar intRegfileWrites;
722 //number of float register file accesses
723 Stats::Scalar fpRegfileReads;
724 Stats::Scalar fpRegfileWrites;
627 /** The register file. */
628 PhysRegFile regFile;
629
630 /** The free list. */
631 typename CPUPolicy::FreeList freeList;
632
633 /** The rename map. */
634 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];

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801 Stats::Formula totalIpc;
802
803 //number of integer register file accesses
804 Stats::Scalar intRegfileReads;
805 Stats::Scalar intRegfileWrites;
806 //number of float register file accesses
807 Stats::Scalar fpRegfileReads;
808 Stats::Scalar fpRegfileWrites;
809 //number of vector register file accesses
810 mutable Stats::Scalar vecRegfileReads;
811 Stats::Scalar vecRegfileWrites;
725 //number of CC register file accesses
726 Stats::Scalar ccRegfileReads;
727 Stats::Scalar ccRegfileWrites;
728 //number of misc
729 Stats::Scalar miscRegfileReads;
730 Stats::Scalar miscRegfileWrites;
731};
732
733#endif // __CPU_O3_CPU_HH__
812 //number of CC register file accesses
813 Stats::Scalar ccRegfileReads;
814 Stats::Scalar ccRegfileWrites;
815 //number of misc
816 Stats::Scalar miscRegfileReads;
817 Stats::Scalar miscRegfileWrites;
818};
819
820#endif // __CPU_O3_CPU_HH__