cpu.hh (11302:bce9037689b0) | cpu.hh (11331:cd5c48db28e6) |
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1/* 2 * Copyright (c) 2011-2013 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 133 unchanged lines hidden (view full) --- 142 : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch) 143 { } 144 145 protected: 146 147 /** Timing version of receive. Handles setting fetch to the 148 * proper status to start fetching. */ 149 virtual bool recvTimingResp(PacketPtr pkt); | 1/* 2 * Copyright (c) 2011-2013 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 133 unchanged lines hidden (view full) --- 142 : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch) 143 { } 144 145 protected: 146 147 /** Timing version of receive. Handles setting fetch to the 148 * proper status to start fetching. */ 149 virtual bool recvTimingResp(PacketPtr pkt); |
150 virtual void recvTimingSnoopReq(PacketPtr pkt) { } | |
151 152 /** Handles doing a retry of a failed fetch. */ 153 virtual void recvReqRetry(); 154 }; 155 156 /** 157 * DcachePort class for the load/store queue. 158 */ --- 576 unchanged lines hidden --- | 150 151 /** Handles doing a retry of a failed fetch. */ 152 virtual void recvReqRetry(); 153 }; 154 155 /** 156 * DcachePort class for the load/store queue. 157 */ --- 576 unchanged lines hidden --- |