cpu.hh (11168:f98eb2da15a4) cpu.hh (11169:44b5c183c3cd)
1/*
2 * Copyright (c) 2011-2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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260
261 public:
262 /** Constructs a CPU with the given parameters. */
263 FullO3CPU(DerivO3CPUParams *params);
264 /** Destructor. */
265 ~FullO3CPU();
266
267 /** Registers statistics. */
1/*
2 * Copyright (c) 2011-2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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260
261 public:
262 /** Constructs a CPU with the given parameters. */
263 FullO3CPU(DerivO3CPUParams *params);
264 /** Destructor. */
265 ~FullO3CPU();
266
267 /** Registers statistics. */
268 void regStats();
268 void regStats() override;
269
270 ProbePointArg<PacketPtr> *ppInstAccessComplete;
271 ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete;
272
273 /** Register probe points. */
269
270 ProbePointArg<PacketPtr> *ppInstAccessComplete;
271 ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete;
272
273 /** Register probe points. */
274 void regProbePoints();
274 void regProbePoints() override;
275
276 void demapPage(Addr vaddr, uint64_t asn)
277 {
278 this->itb->demapPage(vaddr, asn);
279 this->dtb->demapPage(vaddr, asn);
280 }
281
282 void demapInstPage(Addr vaddr, uint64_t asn)

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290 }
291
292 /** Ticks CPU, calling tick() on each stage, and checking the overall
293 * activity to see if the CPU should deschedule itself.
294 */
295 void tick();
296
297 /** Initialize the CPU */
275
276 void demapPage(Addr vaddr, uint64_t asn)
277 {
278 this->itb->demapPage(vaddr, asn);
279 this->dtb->demapPage(vaddr, asn);
280 }
281
282 void demapInstPage(Addr vaddr, uint64_t asn)

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290 }
291
292 /** Ticks CPU, calling tick() on each stage, and checking the overall
293 * activity to see if the CPU should deschedule itself.
294 */
295 void tick();
296
297 /** Initialize the CPU */
298 void init();
298 void init() override;
299
299
300 void startup();
300 void startup() override;
301
302 /** Returns the Number of Active Threads in the CPU */
303 int numActiveThreads()
304 { return activeThreads.size(); }
305
306 /** Add Thread to Active Threads List */
307 void activateThread(ThreadID tid);
308
309 /** Remove Thread from Active Threads List */
310 void deactivateThread(ThreadID tid);
311
312 /** Setup CPU to insert a thread's context */
313 void insertThread(ThreadID tid);
314
315 /** Remove all of a thread's context from CPU */
316 void removeThread(ThreadID tid);
317
318 /** Count the Total Instructions Committed in the CPU. */
301
302 /** Returns the Number of Active Threads in the CPU */
303 int numActiveThreads()
304 { return activeThreads.size(); }
305
306 /** Add Thread to Active Threads List */
307 void activateThread(ThreadID tid);
308
309 /** Remove Thread from Active Threads List */
310 void deactivateThread(ThreadID tid);
311
312 /** Setup CPU to insert a thread's context */
313 void insertThread(ThreadID tid);
314
315 /** Remove all of a thread's context from CPU */
316 void removeThread(ThreadID tid);
317
318 /** Count the Total Instructions Committed in the CPU. */
319 virtual Counter totalInsts() const;
319 Counter totalInsts() const override;
320
321 /** Count the Total Ops (including micro ops) committed in the CPU. */
320
321 /** Count the Total Ops (including micro ops) committed in the CPU. */
322 virtual Counter totalOps() const;
322 Counter totalOps() const override;
323
324 /** Add Thread to Active Threads List. */
323
324 /** Add Thread to Active Threads List. */
325 void activateContext(ThreadID tid);
325 void activateContext(ThreadID tid) override;
326
327 /** Remove Thread from Active Threads List */
326
327 /** Remove Thread from Active Threads List */
328 void suspendContext(ThreadID tid);
328 void suspendContext(ThreadID tid) override;
329
330 /** Remove Thread from Active Threads List &&
331 * Remove Thread Context from CPU.
332 */
329
330 /** Remove Thread from Active Threads List &&
331 * Remove Thread Context from CPU.
332 */
333 void haltContext(ThreadID tid);
333 void haltContext(ThreadID tid) override;
334
335 /** Update The Order In Which We Process Threads. */
336 void updateThreadPriority();
337
338 /** Is the CPU draining? */
339 bool isDraining() const { return drainState() == DrainState::Draining; }
340
341 void serializeThread(CheckpointOut &cp, ThreadID tid) const override;

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359 *
360 * Commit calls this method to inform the pipeline that it has
361 * reached a point where it is not executed microcode and is about
362 * to squash uncommitted instructions to fully drain the pipeline.
363 */
364 void commitDrained(ThreadID tid);
365
366 /** Switches out this CPU. */
334
335 /** Update The Order In Which We Process Threads. */
336 void updateThreadPriority();
337
338 /** Is the CPU draining? */
339 bool isDraining() const { return drainState() == DrainState::Draining; }
340
341 void serializeThread(CheckpointOut &cp, ThreadID tid) const override;

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359 *
360 * Commit calls this method to inform the pipeline that it has
361 * reached a point where it is not executed microcode and is about
362 * to squash uncommitted instructions to fully drain the pipeline.
363 */
364 void commitDrained(ThreadID tid);
365
366 /** Switches out this CPU. */
367 virtual void switchOut();
367 void switchOut() override;
368
369 /** Takes over from another CPU. */
368
369 /** Takes over from another CPU. */
370 virtual void takeOverFrom(BaseCPU *oldCPU);
370 void takeOverFrom(BaseCPU *oldCPU) override;
371
371
372 void verifyMemoryMode() const;
372 void verifyMemoryMode() const override;
373
374 /** Get the current instruction sequence number, and increment it. */
375 InstSeqNum getAndIncrementInstSeq()
376 { return globalSeqNum++; }
377
378 /** Traps to handle given fault. */
379 void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst);
380

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387 Fault getInterrupts();
388
389 /** Processes any an interrupt fault. */
390 void processInterrupts(const Fault &interrupt);
391
392 /** Halts the CPU. */
393 void halt() { panic("Halt not implemented!\n"); }
394
373
374 /** Get the current instruction sequence number, and increment it. */
375 InstSeqNum getAndIncrementInstSeq()
376 { return globalSeqNum++; }
377
378 /** Traps to handle given fault. */
379 void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst);
380

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387 Fault getInterrupts();
388
389 /** Processes any an interrupt fault. */
390 void processInterrupts(const Fault &interrupt);
391
392 /** Halts the CPU. */
393 void halt() { panic("Halt not implemented!\n"); }
394
395 /** Check if this address is a valid instruction address. */
396 bool validInstAddr(Addr addr) { return true; }
397
398 /** Check if this address is a valid data address. */
399 bool validDataAddr(Addr addr) { return true; }
400
401 /** Register accessors. Index refers to the physical register index. */
402
403 /** Reads a miscellaneous register. */
404 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
405
406 /** Reads a misc. register, including any side effects the read
407 * might have as defined by the architecture.
408 */

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694 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
695 uint8_t *data, int store_idx)
696 {
697 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
698 data, store_idx);
699 }
700
701 /** Used by the fetch unit to get a hold of the instruction port. */
395 /** Register accessors. Index refers to the physical register index. */
396
397 /** Reads a miscellaneous register. */
398 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
399
400 /** Reads a misc. register, including any side effects the read
401 * might have as defined by the architecture.
402 */

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688 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
689 uint8_t *data, int store_idx)
690 {
691 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
692 data, store_idx);
693 }
694
695 /** Used by the fetch unit to get a hold of the instruction port. */
702 virtual MasterPort &getInstPort() { return icachePort; }
696 MasterPort &getInstPort() override { return icachePort; }
703
704 /** Get the dcache port (used to find block size for translations). */
697
698 /** Get the dcache port (used to find block size for translations). */
705 virtual MasterPort &getDataPort() { return dcachePort; }
699 MasterPort &getDataPort() override { return dcachePort; }
706
707 /** Stat for total number of times the CPU is descheduled. */
708 Stats::Scalar timesIdled;
709 /** Stat for total number of cycles the CPU spends descheduled. */
710 Stats::Scalar idleCycles;
711 /** Stat for total number of cycles the CPU spends descheduled due to a
712 * quiesce operation or waiting for an interrupt. */
713 Stats::Scalar quiesceCycles;

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701 /** Stat for total number of times the CPU is descheduled. */
702 Stats::Scalar timesIdled;
703 /** Stat for total number of cycles the CPU spends descheduled. */
704 Stats::Scalar idleCycles;
705 /** Stat for total number of cycles the CPU spends descheduled due to a
706 * quiesce operation or waiting for an interrupt. */
707 Stats::Scalar quiesceCycles;

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