| cpu.hh (10934:5af8f40d8f2c) | cpu.hh (10935:acd48ddd725f) |
|---|---|
| 1/* 2 * Copyright (c) 2011-2013 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 413 unchanged lines hidden (view full) --- 422 uint64_t readIntReg(int reg_idx); 423 424 TheISA::FloatReg readFloatReg(int reg_idx); 425 426 TheISA::FloatRegBits readFloatRegBits(int reg_idx); 427 428 TheISA::CCReg readCCReg(int reg_idx); 429 | 1/* 2 * Copyright (c) 2011-2013 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 413 unchanged lines hidden (view full) --- 422 uint64_t readIntReg(int reg_idx); 423 424 TheISA::FloatReg readFloatReg(int reg_idx); 425 426 TheISA::FloatRegBits readFloatRegBits(int reg_idx); 427 428 TheISA::CCReg readCCReg(int reg_idx); 429 |
| 430 const TheISA::VectorReg &readVectorReg(int reg_idx); 431 | |
| 432 void setIntReg(int reg_idx, uint64_t val); 433 434 void setFloatReg(int reg_idx, TheISA::FloatReg val); 435 436 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 437 438 void setCCReg(int reg_idx, TheISA::CCReg val); 439 | 430 void setIntReg(int reg_idx, uint64_t val); 431 432 void setFloatReg(int reg_idx, TheISA::FloatReg val); 433 434 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 435 436 void setCCReg(int reg_idx, TheISA::CCReg val); 437 |
| 440 void setVectorReg(int reg_idx, const TheISA::VectorReg &val); 441 | |
| 442 uint64_t readArchIntReg(int reg_idx, ThreadID tid); 443 444 float readArchFloatReg(int reg_idx, ThreadID tid); 445 446 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); 447 448 TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid); 449 | 438 uint64_t readArchIntReg(int reg_idx, ThreadID tid); 439 440 float readArchFloatReg(int reg_idx, ThreadID tid); 441 442 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); 443 444 TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid); 445 |
| 450 const TheISA::VectorReg &readArchVectorReg(int reg_idx, ThreadID tid); 451 | |
| 452 /** Architectural register accessors. Looks up in the commit 453 * rename table to obtain the true physical index of the 454 * architected register first, then accesses that physical 455 * register. 456 */ 457 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); 458 459 void setArchFloatReg(int reg_idx, float val, ThreadID tid); 460 461 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); 462 463 void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid); 464 | 446 /** Architectural register accessors. Looks up in the commit 447 * rename table to obtain the true physical index of the 448 * architected register first, then accesses that physical 449 * register. 450 */ 451 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); 452 453 void setArchFloatReg(int reg_idx, float val, ThreadID tid); 454 455 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); 456 457 void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid); 458 |
| 465 void setArchVectorReg(int reg_idx, const TheISA::VectorReg &val, 466 ThreadID tid); 467 | |
| 468 /** Sets the commit PC state of a specific thread. */ 469 void pcState(const TheISA::PCState &newPCState, ThreadID tid); 470 471 /** Reads the commit PC state of a specific thread. */ 472 TheISA::PCState pcState(ThreadID tid); 473 474 /** Reads the commit PC of a specific thread. */ 475 Addr instAddr(ThreadID tid); --- 262 unchanged lines hidden (view full) --- 738 Stats::Scalar intRegfileReads; 739 Stats::Scalar intRegfileWrites; 740 //number of float register file accesses 741 Stats::Scalar fpRegfileReads; 742 Stats::Scalar fpRegfileWrites; 743 //number of CC register file accesses 744 Stats::Scalar ccRegfileReads; 745 Stats::Scalar ccRegfileWrites; | 459 /** Sets the commit PC state of a specific thread. */ 460 void pcState(const TheISA::PCState &newPCState, ThreadID tid); 461 462 /** Reads the commit PC state of a specific thread. */ 463 TheISA::PCState pcState(ThreadID tid); 464 465 /** Reads the commit PC of a specific thread. */ 466 Addr instAddr(ThreadID tid); --- 262 unchanged lines hidden (view full) --- 729 Stats::Scalar intRegfileReads; 730 Stats::Scalar intRegfileWrites; 731 //number of float register file accesses 732 Stats::Scalar fpRegfileReads; 733 Stats::Scalar fpRegfileWrites; 734 //number of CC register file accesses 735 Stats::Scalar ccRegfileReads; 736 Stats::Scalar ccRegfileWrites; |
| 746 //number of integer register file accesses 747 Stats::Scalar vectorRegfileReads; 748 Stats::Scalar vectorRegfileWrites; | |
| 749 //number of misc 750 Stats::Scalar miscRegfileReads; 751 Stats::Scalar miscRegfileWrites; 752}; 753 754#endif // __CPU_O3_CPU_HH__ | 737 //number of misc 738 Stats::Scalar miscRegfileReads; 739 Stats::Scalar miscRegfileWrites; 740}; 741 742#endif // __CPU_O3_CPU_HH__ |