cpu.hh (10417:710ee116eb68) cpu.hh (10529:05b5a6cf3521)
1/*
2 * Copyright (c) 2011-2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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157 * DcachePort class for the load/store queue.
158 */
159 class DcachePort : public MasterPort
160 {
161 protected:
162
163 /** Pointer to LSQ. */
164 LSQ<Impl> *lsq;
1/*
2 * Copyright (c) 2011-2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 148 unchanged lines hidden (view full) ---

157 * DcachePort class for the load/store queue.
158 */
159 class DcachePort : public MasterPort
160 {
161 protected:
162
163 /** Pointer to LSQ. */
164 LSQ<Impl> *lsq;
165 FullO3CPU<Impl> *cpu;
165
166 public:
167 /** Default constructor. */
168 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
166
167 public:
168 /** Default constructor. */
169 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
169 : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq)
170 : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq),
171 cpu(_cpu)
170 { }
171
172 protected:
173
174 /** Timing version of receive. Handles writing back and
175 * completing the load or store that has returned from
176 * memory. */
177 virtual bool recvTimingResp(PacketPtr pkt);

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173
174 protected:
175
176 /** Timing version of receive. Handles writing back and
177 * completing the load or store that has returned from
178 * memory. */
179 virtual bool recvTimingResp(PacketPtr pkt);

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