1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 * Rick Strong
44 */
45
46#ifndef __CPU_O3_CPU_HH__
47#define __CPU_O3_CPU_HH__
48
49#include <iostream>
50#include <list>
51#include <queue>
52#include <set>
53#include <vector>
54
55#include "arch/types.hh"
56#include "base/statistics.hh"
57#include "config/the_isa.hh"
58#include "config/use_checker.hh"
58#include "cpu/o3/comm.hh"
59#include "cpu/o3/cpu_policy.hh"
60#include "cpu/o3/scoreboard.hh"
61#include "cpu/o3/thread_state.hh"
62#include "cpu/activity.hh"
63#include "cpu/base.hh"
64#include "cpu/simple_thread.hh"
65#include "cpu/timebuf.hh"
66//#include "cpu/o3/thread_context.hh"
67#include "params/DerivO3CPU.hh"
68#include "sim/process.hh"
69
70template <class>
71class Checker;
72class ThreadContext;
73template <class>
74class O3ThreadContext;
75
76class Checkpoint;
77class MemObject;
78class Process;
79
80struct BaseCPUParams;
81
82class BaseO3CPU : public BaseCPU
83{
84 //Stuff that's pretty ISA independent will go here.
85 public:
86 BaseO3CPU(BaseCPUParams *params);
87
88 void regStats();
89};
90
91/**
92 * FullO3CPU class, has each of the stages (fetch through commit)
93 * within it, as well as all of the time buffers between stages. The
94 * tick() function for the CPU is defined here.
95 */
96template <class Impl>
97class FullO3CPU : public BaseO3CPU
98{
99 public:
100 // Typedefs from the Impl here.
101 typedef typename Impl::CPUPol CPUPolicy;
102 typedef typename Impl::DynInstPtr DynInstPtr;
103 typedef typename Impl::O3CPU O3CPU;
104
105 typedef O3ThreadState<Impl> ImplState;
106 typedef O3ThreadState<Impl> Thread;
107
108 typedef typename std::list<DynInstPtr>::iterator ListIt;
109
110 friend class O3ThreadContext<Impl>;
111
112 public:
113 enum Status {
114 Running,
115 Idle,
116 Halted,
117 Blocked,
118 SwitchedOut
119 };
120
121 TheISA::TLB * itb;
122 TheISA::TLB * dtb;
123
124 /** Overall CPU status. */
125 Status _status;
126
127 /** Per-thread status in CPU, used for SMT. */
128 Status _threadStatus[Impl::MaxThreads];
129
130 private:
131
132 /**
133 * IcachePort class for instruction fetch.
134 */
135 class IcachePort : public CpuPort
136 {
137 protected:
138 /** Pointer to fetch. */
139 DefaultFetch<Impl> *fetch;
140
141 public:
142 /** Default constructor. */
143 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
144 : CpuPort(_fetch->name() + "-iport", _cpu), fetch(_fetch)
145 { }
146
147 protected:
148
149 /** Timing version of receive. Handles setting fetch to the
150 * proper status to start fetching. */
151 virtual bool recvTiming(PacketPtr pkt);
152
153 /** Handles doing a retry of a failed fetch. */
154 virtual void recvRetry();
155 };
156
157 /**
158 * DcachePort class for the load/store queue.
159 */
160 class DcachePort : public CpuPort
161 {
162 protected:
163
164 /** Pointer to LSQ. */
165 LSQ<Impl> *lsq;
166
167 public:
168 /** Default constructor. */
169 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
170 : CpuPort(_lsq->name() + "-dport", _cpu), lsq(_lsq)
171 { }
172
173 protected:
174
175 /** Timing version of receive. Handles writing back and
176 * completing the load or store that has returned from
177 * memory. */
178 virtual bool recvTiming(PacketPtr pkt);
179
180 /** Handles doing a retry of the previous send. */
181 virtual void recvRetry();
182
183 /**
184 * As this CPU requires snooping to maintain the load store queue
185 * change the behaviour from the base CPU port.
186 *
187 * @return true since we have to snoop
188 */
189 virtual bool isSnooping()
190 { return true; }
191 };
192
193 class TickEvent : public Event
194 {
195 private:
196 /** Pointer to the CPU. */
197 FullO3CPU<Impl> *cpu;
198
199 public:
200 /** Constructs a tick event. */
201 TickEvent(FullO3CPU<Impl> *c);
202
203 /** Processes a tick event, calling tick() on the CPU. */
204 void process();
205 /** Returns the description of the tick event. */
206 const char *description() const;
207 };
208
209 /** The tick event used for scheduling CPU ticks. */
210 TickEvent tickEvent;
211
212 /** Schedule tick event, regardless of its current state. */
213 void scheduleTickEvent(int delay)
214 {
215 if (tickEvent.squashed())
216 reschedule(tickEvent, nextCycle(curTick() + ticks(delay)));
217 else if (!tickEvent.scheduled())
218 schedule(tickEvent, nextCycle(curTick() + ticks(delay)));
219 }
220
221 /** Unschedule tick event, regardless of its current state. */
222 void unscheduleTickEvent()
223 {
224 if (tickEvent.scheduled())
225 tickEvent.squash();
226 }
227
228 class ActivateThreadEvent : public Event
229 {
230 private:
231 /** Number of Thread to Activate */
232 ThreadID tid;
233
234 /** Pointer to the CPU. */
235 FullO3CPU<Impl> *cpu;
236
237 public:
238 /** Constructs the event. */
239 ActivateThreadEvent();
240
241 /** Initialize Event */
242 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
243
244 /** Processes the event, calling activateThread() on the CPU. */
245 void process();
246
247 /** Returns the description of the event. */
248 const char *description() const;
249 };
250
251 /** Schedule thread to activate , regardless of its current state. */
252 void
253 scheduleActivateThreadEvent(ThreadID tid, int delay)
254 {
255 // Schedule thread to activate, regardless of its current state.
256 if (activateThreadEvent[tid].squashed())
257 reschedule(activateThreadEvent[tid],
258 nextCycle(curTick() + ticks(delay)));
259 else if (!activateThreadEvent[tid].scheduled()) {
260 Tick when = nextCycle(curTick() + ticks(delay));
261
262 // Check if the deallocateEvent is also scheduled, and make
263 // sure they do not happen at same time causing a sleep that
264 // is never woken from.
265 if (deallocateContextEvent[tid].scheduled() &&
266 deallocateContextEvent[tid].when() == when) {
267 when++;
268 }
269
270 schedule(activateThreadEvent[tid], when);
271 }
272 }
273
274 /** Unschedule actiavte thread event, regardless of its current state. */
275 void
276 unscheduleActivateThreadEvent(ThreadID tid)
277 {
278 if (activateThreadEvent[tid].scheduled())
279 activateThreadEvent[tid].squash();
280 }
281
282 /** The tick event used for scheduling CPU ticks. */
283 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
284
285 class DeallocateContextEvent : public Event
286 {
287 private:
288 /** Number of Thread to deactivate */
289 ThreadID tid;
290
291 /** Should the thread be removed from the CPU? */
292 bool remove;
293
294 /** Pointer to the CPU. */
295 FullO3CPU<Impl> *cpu;
296
297 public:
298 /** Constructs the event. */
299 DeallocateContextEvent();
300
301 /** Initialize Event */
302 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
303
304 /** Processes the event, calling activateThread() on the CPU. */
305 void process();
306
307 /** Sets whether the thread should also be removed from the CPU. */
308 void setRemove(bool _remove) { remove = _remove; }
309
310 /** Returns the description of the event. */
311 const char *description() const;
312 };
313
314 /** Schedule cpu to deallocate thread context.*/
315 void
316 scheduleDeallocateContextEvent(ThreadID tid, bool remove, int delay)
317 {
318 // Schedule thread to activate, regardless of its current state.
319 if (deallocateContextEvent[tid].squashed())
320 reschedule(deallocateContextEvent[tid],
321 nextCycle(curTick() + ticks(delay)));
322 else if (!deallocateContextEvent[tid].scheduled())
323 schedule(deallocateContextEvent[tid],
324 nextCycle(curTick() + ticks(delay)));
325 }
326
327 /** Unschedule thread deallocation in CPU */
328 void
329 unscheduleDeallocateContextEvent(ThreadID tid)
330 {
331 if (deallocateContextEvent[tid].scheduled())
332 deallocateContextEvent[tid].squash();
333 }
334
335 /** The tick event used for scheduling CPU ticks. */
336 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
337
338 public:
339 /** Constructs a CPU with the given parameters. */
340 FullO3CPU(DerivO3CPUParams *params);
341 /** Destructor. */
342 ~FullO3CPU();
343
344 /** Registers statistics. */
345 void regStats();
346
347 void demapPage(Addr vaddr, uint64_t asn)
348 {
349 this->itb->demapPage(vaddr, asn);
350 this->dtb->demapPage(vaddr, asn);
351 }
352
353 void demapInstPage(Addr vaddr, uint64_t asn)
354 {
355 this->itb->demapPage(vaddr, asn);
356 }
357
358 void demapDataPage(Addr vaddr, uint64_t asn)
359 {
360 this->dtb->demapPage(vaddr, asn);
361 }
362
363 /** Ticks CPU, calling tick() on each stage, and checking the overall
364 * activity to see if the CPU should deschedule itself.
365 */
366 void tick();
367
368 /** Initialize the CPU */
369 void init();
370
371 /** Returns the Number of Active Threads in the CPU */
372 int numActiveThreads()
373 { return activeThreads.size(); }
374
375 /** Add Thread to Active Threads List */
376 void activateThread(ThreadID tid);
377
378 /** Remove Thread from Active Threads List */
379 void deactivateThread(ThreadID tid);
380
381 /** Setup CPU to insert a thread's context */
382 void insertThread(ThreadID tid);
383
384 /** Remove all of a thread's context from CPU */
385 void removeThread(ThreadID tid);
386
387 /** Count the Total Instructions Committed in the CPU. */
388 virtual Counter totalInsts() const;
389
390 /** Count the Total Ops (including micro ops) committed in the CPU. */
391 virtual Counter totalOps() const;
392
393 /** Add Thread to Active Threads List. */
394 void activateContext(ThreadID tid, int delay);
395
396 /** Remove Thread from Active Threads List */
397 void suspendContext(ThreadID tid);
398
399 /** Remove Thread from Active Threads List &&
400 * Possibly Remove Thread Context from CPU.
401 */
402 bool scheduleDeallocateContext(ThreadID tid, bool remove, int delay = 1);
403
404 /** Remove Thread from Active Threads List &&
405 * Remove Thread Context from CPU.
406 */
407 void haltContext(ThreadID tid);
408
409 /** Activate a Thread When CPU Resources are Available. */
410 void activateWhenReady(ThreadID tid);
411
412 /** Add or Remove a Thread Context in the CPU. */
413 void doContextSwitch();
414
415 /** Update The Order In Which We Process Threads. */
416 void updateThreadPriority();
417
418 /** Serialize state. */
419 virtual void serialize(std::ostream &os);
420
421 /** Unserialize from a checkpoint. */
422 virtual void unserialize(Checkpoint *cp, const std::string &section);
423
424 public:
425 /** Executes a syscall.
426 * @todo: Determine if this needs to be virtual.
427 */
428 void syscall(int64_t callnum, ThreadID tid);
429
430 /** Starts draining the CPU's pipeline of all instructions in
431 * order to stop all memory accesses. */
432 virtual unsigned int drain(Event *drain_event);
433
434 /** Resumes execution after a drain. */
435 virtual void resume();
436
437 /** Signals to this CPU that a stage has completed switching out. */
438 void signalDrained();
439
440 /** Switches out this CPU. */
441 virtual void switchOut();
442
443 /** Takes over from another CPU. */
444 virtual void takeOverFrom(BaseCPU *oldCPU);
445
446 /** Get the current instruction sequence number, and increment it. */
447 InstSeqNum getAndIncrementInstSeq()
448 { return globalSeqNum++; }
449
450 /** Traps to handle given fault. */
451 void trap(Fault fault, ThreadID tid, StaticInstPtr inst);
452
453 /** HW return from error interrupt. */
454 Fault hwrei(ThreadID tid);
455
456 bool simPalCheck(int palFunc, ThreadID tid);
457
458 /** Returns the Fault for any valid interrupt. */
459 Fault getInterrupts();
460
461 /** Processes any an interrupt fault. */
462 void processInterrupts(Fault interrupt);
463
464 /** Halts the CPU. */
465 void halt() { panic("Halt not implemented!\n"); }
466
467 /** Check if this address is a valid instruction address. */
468 bool validInstAddr(Addr addr) { return true; }
469
470 /** Check if this address is a valid data address. */
471 bool validDataAddr(Addr addr) { return true; }
472
473 /** Register accessors. Index refers to the physical register index. */
474
475 /** Reads a miscellaneous register. */
476 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
477
478 /** Reads a misc. register, including any side effects the read
479 * might have as defined by the architecture.
480 */
481 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
482
483 /** Sets a miscellaneous register. */
484 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
485 ThreadID tid);
486
487 /** Sets a misc. register, including any side effects the write
488 * might have as defined by the architecture.
489 */
490 void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
491 ThreadID tid);
492
493 uint64_t readIntReg(int reg_idx);
494
495 TheISA::FloatReg readFloatReg(int reg_idx);
496
497 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
498
499 void setIntReg(int reg_idx, uint64_t val);
500
501 void setFloatReg(int reg_idx, TheISA::FloatReg val);
502
503 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
504
505 uint64_t readArchIntReg(int reg_idx, ThreadID tid);
506
507 float readArchFloatReg(int reg_idx, ThreadID tid);
508
509 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
510
511 /** Architectural register accessors. Looks up in the commit
512 * rename table to obtain the true physical index of the
513 * architected register first, then accesses that physical
514 * register.
515 */
516 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
517
518 void setArchFloatReg(int reg_idx, float val, ThreadID tid);
519
520 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
521
522 /** Sets the commit PC state of a specific thread. */
523 void pcState(const TheISA::PCState &newPCState, ThreadID tid);
524
525 /** Reads the commit PC state of a specific thread. */
526 TheISA::PCState pcState(ThreadID tid);
527
528 /** Reads the commit PC of a specific thread. */
529 Addr instAddr(ThreadID tid);
530
531 /** Reads the commit micro PC of a specific thread. */
532 MicroPC microPC(ThreadID tid);
533
534 /** Reads the next PC of a specific thread. */
535 Addr nextInstAddr(ThreadID tid);
536
537 /** Initiates a squash of all in-flight instructions for a given
538 * thread. The source of the squash is an external update of
539 * state through the TC.
540 */
541 void squashFromTC(ThreadID tid);
542
543 /** Function to add instruction onto the head of the list of the
544 * instructions. Used when new instructions are fetched.
545 */
546 ListIt addInst(DynInstPtr &inst);
547
548 /** Function to tell the CPU that an instruction has completed. */
549 void instDone(ThreadID tid, DynInstPtr &inst);
550
551 /** Remove an instruction from the front end of the list. There's
552 * no restriction on location of the instruction.
553 */
554 void removeFrontInst(DynInstPtr &inst);
555
556 /** Remove all instructions that are not currently in the ROB.
557 * There's also an option to not squash delay slot instructions.*/
558 void removeInstsNotInROB(ThreadID tid);
559
560 /** Remove all instructions younger than the given sequence number. */
561 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
562
563 /** Removes the instruction pointed to by the iterator. */
564 inline void squashInstIt(const ListIt &instIt, ThreadID tid);
565
566 /** Cleans up all instructions on the remove list. */
567 void cleanUpRemovedInsts();
568
569 /** Debug function to print all instructions on the list. */
570 void dumpInsts();
571
572 public:
573#ifndef NDEBUG
574 /** Count of total number of dynamic instructions in flight. */
575 int instcount;
576#endif
577
578 /** List of all the instructions in flight. */
579 std::list<DynInstPtr> instList;
580
581 /** List of all the instructions that will be removed at the end of this
582 * cycle.
583 */
584 std::queue<ListIt> removeList;
585
586#ifdef DEBUG
587 /** Debug structure to keep track of the sequence numbers still in
588 * flight.
589 */
590 std::set<InstSeqNum> snList;
591#endif
592
593 /** Records if instructions need to be removed this cycle due to
594 * being retired or squashed.
595 */
596 bool removeInstsThisCycle;
597
598 protected:
599 /** The fetch stage. */
600 typename CPUPolicy::Fetch fetch;
601
602 /** The decode stage. */
603 typename CPUPolicy::Decode decode;
604
605 /** The dispatch stage. */
606 typename CPUPolicy::Rename rename;
607
608 /** The issue/execute/writeback stages. */
609 typename CPUPolicy::IEW iew;
610
611 /** The commit stage. */
612 typename CPUPolicy::Commit commit;
613
614 /** The register file. */
615 typename CPUPolicy::RegFile regFile;
616
617 /** The free list. */
618 typename CPUPolicy::FreeList freeList;
619
620 /** The rename map. */
621 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
622
623 /** The commit rename map. */
624 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
625
626 /** The re-order buffer. */
627 typename CPUPolicy::ROB rob;
628
629 /** Active Threads List */
630 std::list<ThreadID> activeThreads;
631
632 /** Integer Register Scoreboard */
633 Scoreboard scoreboard;
634
635 TheISA::ISA isa[Impl::MaxThreads];
636
637 /** Instruction port. Note that it has to appear after the fetch stage. */
638 IcachePort icachePort;
639
640 /** Data port. Note that it has to appear after the iew stages */
641 DcachePort dcachePort;
642
643 public:
644 /** Enum to give each stage a specific index, so when calling
645 * activateStage() or deactivateStage(), they can specify which stage
646 * is being activated/deactivated.
647 */
648 enum StageIdx {
649 FetchIdx,
650 DecodeIdx,
651 RenameIdx,
652 IEWIdx,
653 CommitIdx,
654 NumStages };
655
656 /** Typedefs from the Impl to get the structs that each of the
657 * time buffers should use.
658 */
659 typedef typename CPUPolicy::TimeStruct TimeStruct;
660
661 typedef typename CPUPolicy::FetchStruct FetchStruct;
662
663 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
664
665 typedef typename CPUPolicy::RenameStruct RenameStruct;
666
667 typedef typename CPUPolicy::IEWStruct IEWStruct;
668
669 /** The main time buffer to do backwards communication. */
670 TimeBuffer<TimeStruct> timeBuffer;
671
672 /** The fetch stage's instruction queue. */
673 TimeBuffer<FetchStruct> fetchQueue;
674
675 /** The decode stage's instruction queue. */
676 TimeBuffer<DecodeStruct> decodeQueue;
677
678 /** The rename stage's instruction queue. */
679 TimeBuffer<RenameStruct> renameQueue;
680
681 /** The IEW stage's instruction queue. */
682 TimeBuffer<IEWStruct> iewQueue;
683
684 private:
685 /** The activity recorder; used to tell if the CPU has any
686 * activity remaining or if it can go to idle and deschedule
687 * itself.
688 */
689 ActivityRecorder activityRec;
690
691 public:
692 /** Records that there was time buffer activity this cycle. */
693 void activityThisCycle() { activityRec.activity(); }
694
695 /** Changes a stage's status to active within the activity recorder. */
696 void activateStage(const StageIdx idx)
697 { activityRec.activateStage(idx); }
698
699 /** Changes a stage's status to inactive within the activity recorder. */
700 void deactivateStage(const StageIdx idx)
701 { activityRec.deactivateStage(idx); }
702
703 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
704 void wakeCPU();
705
706 virtual void wakeup();
707
708 /** Gets a free thread id. Use if thread ids change across system. */
709 ThreadID getFreeTid();
710
711 public:
712 /** Returns a pointer to a thread context. */
713 ThreadContext *
714 tcBase(ThreadID tid)
715 {
716 return thread[tid]->getTC();
717 }
718
719 /** The global sequence number counter. */
720 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
721
723#if USE_CHECKER
722 /** Pointer to the checker, which can dynamically verify
723 * instruction results at run time. This can be set to NULL if it
724 * is not being used.
725 */
726 Checker<Impl> *checker;
729#endif
727
728 /** Pointer to the system. */
729 System *system;
730
731 /** Event to call process() on once draining has completed. */
732 Event *drainEvent;
733
734 /** Counter of how many stages have completed draining. */
735 int drainCount;
736
737 /** Pointers to all of the threads in the CPU. */
738 std::vector<Thread *> thread;
739
740 /** Whether or not the CPU should defer its registration. */
741 bool deferRegistration;
742
743 /** Is there a context switch pending? */
744 bool contextSwitch;
745
746 /** Threads Scheduled to Enter CPU */
747 std::list<int> cpuWaitList;
748
749 /** The cycle that the CPU was last running, used for statistics. */
750 Tick lastRunningCycle;
751
752 /** The cycle that the CPU was last activated by a new thread*/
753 Tick lastActivatedCycle;
754
755 /** Mapping for system thread id to cpu id */
756 std::map<ThreadID, unsigned> threadMap;
757
758 /** Available thread ids in the cpu*/
759 std::vector<ThreadID> tids;
760
761 /** CPU read function, forwards read to LSQ. */
762 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
763 uint8_t *data, int load_idx)
764 {
765 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh,
766 data, load_idx);
767 }
768
769 /** CPU write function, forwards write to LSQ. */
770 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
771 uint8_t *data, int store_idx)
772 {
773 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
774 data, store_idx);
775 }
776
777 /** Used by the fetch unit to get a hold of the instruction port. */
778 virtual CpuPort &getInstPort() { return icachePort; }
779
780 /** Get the dcache port (used to find block size for translations). */
781 virtual CpuPort &getDataPort() { return dcachePort; }
782
783 Addr lockAddr;
784
785 /** Temporary fix for the lock flag, works in the UP case. */
786 bool lockFlag;
787
788 /** Stat for total number of times the CPU is descheduled. */
789 Stats::Scalar timesIdled;
790 /** Stat for total number of cycles the CPU spends descheduled. */
791 Stats::Scalar idleCycles;
792 /** Stat for total number of cycles the CPU spends descheduled due to a
793 * quiesce operation or waiting for an interrupt. */
794 Stats::Scalar quiesceCycles;
795 /** Stat for the number of committed instructions per thread. */
796 Stats::Vector committedInsts;
797 /** Stat for the number of committed ops (including micro ops) per thread. */
798 Stats::Vector committedOps;
799 /** Stat for the total number of committed instructions. */
800 Stats::Scalar totalCommittedInsts;
801 /** Stat for the CPI per thread. */
802 Stats::Formula cpi;
803 /** Stat for the total CPI. */
804 Stats::Formula totalCpi;
805 /** Stat for the IPC per thread. */
806 Stats::Formula ipc;
807 /** Stat for the total IPC. */
808 Stats::Formula totalIpc;
809
810 //number of integer register file accesses
811 Stats::Scalar intRegfileReads;
812 Stats::Scalar intRegfileWrites;
813 //number of float register file accesses
814 Stats::Scalar fpRegfileReads;
815 Stats::Scalar fpRegfileWrites;
816 //number of misc
817 Stats::Scalar miscRegfileReads;
818 Stats::Scalar miscRegfileWrites;
819};
820
821#endif // __CPU_O3_CPU_HH__