1/*
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2 * Copyright (c) 2011-2013 ARM Limited
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2 * Copyright (c) 2011-2013, 2016 ARM Limited |
3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2004-2005 The Regents of The University of Michigan 16 * Copyright (c) 2011 Regents of the University of California 17 * All rights reserved. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions are 21 * met: redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer; 23 * redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution; 26 * neither the name of the copyright holders nor the names of its 27 * contributors may be used to endorse or promote products derived from 28 * this software without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 * Authors: Kevin Lim 43 * Korey Sewell 44 * Rick Strong 45 */ 46 47#ifndef __CPU_O3_CPU_HH__ 48#define __CPU_O3_CPU_HH__ 49 50#include <iostream> 51#include <list> 52#include <queue> 53#include <set> 54#include <vector> 55
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56#include "arch/generic/types.hh" |
57#include "arch/types.hh" 58#include "base/statistics.hh" 59#include "config/the_isa.hh" 60#include "cpu/o3/comm.hh" 61#include "cpu/o3/cpu_policy.hh" 62#include "cpu/o3/scoreboard.hh" 63#include "cpu/o3/thread_state.hh" 64#include "cpu/activity.hh" 65#include "cpu/base.hh" 66#include "cpu/simple_thread.hh" 67#include "cpu/timebuf.hh" 68//#include "cpu/o3/thread_context.hh" 69#include "params/DerivO3CPU.hh" 70#include "sim/process.hh" 71 72template <class> 73class Checker; 74class ThreadContext; 75template <class> 76class O3ThreadContext; 77 78class Checkpoint; 79class MemObject; 80class Process; 81 82struct BaseCPUParams; 83 84class BaseO3CPU : public BaseCPU 85{ 86 //Stuff that's pretty ISA independent will go here. 87 public: 88 BaseO3CPU(BaseCPUParams *params); 89 90 void regStats(); 91}; 92 93/** 94 * FullO3CPU class, has each of the stages (fetch through commit) 95 * within it, as well as all of the time buffers between stages. The 96 * tick() function for the CPU is defined here. 97 */ 98template <class Impl> 99class FullO3CPU : public BaseO3CPU 100{ 101 public: 102 // Typedefs from the Impl here. 103 typedef typename Impl::CPUPol CPUPolicy; 104 typedef typename Impl::DynInstPtr DynInstPtr; 105 typedef typename Impl::O3CPU O3CPU; 106
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107 using VecElem = TheISA::VecElem; 108 using VecRegContainer = TheISA::VecRegContainer; 109 |
110 typedef O3ThreadState<Impl> ImplState; 111 typedef O3ThreadState<Impl> Thread; 112 113 typedef typename std::list<DynInstPtr>::iterator ListIt; 114 115 friend class O3ThreadContext<Impl>; 116 117 public: 118 enum Status { 119 Running, 120 Idle, 121 Halted, 122 Blocked, 123 SwitchedOut 124 }; 125 126 TheISA::TLB * itb; 127 TheISA::TLB * dtb; 128 129 /** Overall CPU status. */ 130 Status _status; 131 132 private: 133 134 /** 135 * IcachePort class for instruction fetch. 136 */ 137 class IcachePort : public MasterPort 138 { 139 protected: 140 /** Pointer to fetch. */ 141 DefaultFetch<Impl> *fetch; 142 143 public: 144 /** Default constructor. */ 145 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu) 146 : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch) 147 { } 148 149 protected: 150 151 /** Timing version of receive. Handles setting fetch to the 152 * proper status to start fetching. */ 153 virtual bool recvTimingResp(PacketPtr pkt); 154 155 /** Handles doing a retry of a failed fetch. */ 156 virtual void recvReqRetry(); 157 }; 158 159 /** 160 * DcachePort class for the load/store queue. 161 */ 162 class DcachePort : public MasterPort 163 { 164 protected: 165 166 /** Pointer to LSQ. */ 167 LSQ<Impl> *lsq; 168 FullO3CPU<Impl> *cpu; 169 170 public: 171 /** Default constructor. */ 172 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu) 173 : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq), 174 cpu(_cpu) 175 { } 176 177 protected: 178 179 /** Timing version of receive. Handles writing back and 180 * completing the load or store that has returned from 181 * memory. */ 182 virtual bool recvTimingResp(PacketPtr pkt); 183 virtual void recvTimingSnoopReq(PacketPtr pkt); 184 185 virtual void recvFunctionalSnoop(PacketPtr pkt) 186 { 187 // @todo: Is there a need for potential invalidation here? 188 } 189 190 /** Handles doing a retry of the previous send. */ 191 virtual void recvReqRetry(); 192 193 /** 194 * As this CPU requires snooping to maintain the load store queue 195 * change the behaviour from the base CPU port. 196 * 197 * @return true since we have to snoop 198 */ 199 virtual bool isSnooping() const { return true; } 200 }; 201 202 class TickEvent : public Event 203 { 204 private: 205 /** Pointer to the CPU. */ 206 FullO3CPU<Impl> *cpu; 207 208 public: 209 /** Constructs a tick event. */ 210 TickEvent(FullO3CPU<Impl> *c); 211 212 /** Processes a tick event, calling tick() on the CPU. */ 213 void process(); 214 /** Returns the description of the tick event. */ 215 const char *description() const; 216 }; 217 218 /** The tick event used for scheduling CPU ticks. */ 219 TickEvent tickEvent; 220 221 /** Schedule tick event, regardless of its current state. */ 222 void scheduleTickEvent(Cycles delay) 223 { 224 if (tickEvent.squashed()) 225 reschedule(tickEvent, clockEdge(delay)); 226 else if (!tickEvent.scheduled()) 227 schedule(tickEvent, clockEdge(delay)); 228 } 229 230 /** Unschedule tick event, regardless of its current state. */ 231 void unscheduleTickEvent() 232 { 233 if (tickEvent.scheduled()) 234 tickEvent.squash(); 235 } 236 237 /** 238 * Check if the pipeline has drained and signal drain done. 239 * 240 * This method checks if a drain has been requested and if the CPU 241 * has drained successfully (i.e., there are no instructions in 242 * the pipeline). If the CPU has drained, it deschedules the tick 243 * event and signals the drain manager. 244 * 245 * @return False if a drain hasn't been requested or the CPU 246 * hasn't drained, true otherwise. 247 */ 248 bool tryDrain(); 249 250 /** 251 * Perform sanity checks after a drain. 252 * 253 * This method is called from drain() when it has determined that 254 * the CPU is fully drained when gem5 is compiled with the NDEBUG 255 * macro undefined. The intention of this method is to do more 256 * extensive tests than the isDrained() method to weed out any 257 * draining bugs. 258 */ 259 void drainSanityCheck() const; 260 261 /** Check if a system is in a drained state. */ 262 bool isDrained() const; 263 264 public: 265 /** Constructs a CPU with the given parameters. */ 266 FullO3CPU(DerivO3CPUParams *params); 267 /** Destructor. */ 268 ~FullO3CPU(); 269 270 /** Registers statistics. */ 271 void regStats() override; 272 273 ProbePointArg<PacketPtr> *ppInstAccessComplete; 274 ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete; 275 276 /** Register probe points. */ 277 void regProbePoints() override; 278 279 void demapPage(Addr vaddr, uint64_t asn) 280 { 281 this->itb->demapPage(vaddr, asn); 282 this->dtb->demapPage(vaddr, asn); 283 } 284 285 void demapInstPage(Addr vaddr, uint64_t asn) 286 { 287 this->itb->demapPage(vaddr, asn); 288 } 289 290 void demapDataPage(Addr vaddr, uint64_t asn) 291 { 292 this->dtb->demapPage(vaddr, asn); 293 } 294 295 /** Ticks CPU, calling tick() on each stage, and checking the overall 296 * activity to see if the CPU should deschedule itself. 297 */ 298 void tick(); 299 300 /** Initialize the CPU */ 301 void init() override; 302 303 void startup() override; 304 305 /** Returns the Number of Active Threads in the CPU */ 306 int numActiveThreads() 307 { return activeThreads.size(); } 308 309 /** Add Thread to Active Threads List */ 310 void activateThread(ThreadID tid); 311 312 /** Remove Thread from Active Threads List */ 313 void deactivateThread(ThreadID tid); 314 315 /** Setup CPU to insert a thread's context */ 316 void insertThread(ThreadID tid); 317 318 /** Remove all of a thread's context from CPU */ 319 void removeThread(ThreadID tid); 320 321 /** Count the Total Instructions Committed in the CPU. */ 322 Counter totalInsts() const override; 323 324 /** Count the Total Ops (including micro ops) committed in the CPU. */ 325 Counter totalOps() const override; 326 327 /** Add Thread to Active Threads List. */ 328 void activateContext(ThreadID tid) override; 329 330 /** Remove Thread from Active Threads List */ 331 void suspendContext(ThreadID tid) override; 332 333 /** Remove Thread from Active Threads List && 334 * Remove Thread Context from CPU. 335 */ 336 void haltContext(ThreadID tid) override; 337 338 /** Update The Order In Which We Process Threads. */ 339 void updateThreadPriority(); 340 341 /** Is the CPU draining? */ 342 bool isDraining() const { return drainState() == DrainState::Draining; } 343 344 void serializeThread(CheckpointOut &cp, ThreadID tid) const override; 345 void unserializeThread(CheckpointIn &cp, ThreadID tid) override; 346 347 public: 348 /** Executes a syscall. 349 * @todo: Determine if this needs to be virtual. 350 */ 351 void syscall(int64_t callnum, ThreadID tid, Fault *fault); 352 353 /** Starts draining the CPU's pipeline of all instructions in 354 * order to stop all memory accesses. */ 355 DrainState drain() override; 356 357 /** Resumes execution after a drain. */ 358 void drainResume() override; 359 360 /** 361 * Commit has reached a safe point to drain a thread. 362 * 363 * Commit calls this method to inform the pipeline that it has 364 * reached a point where it is not executed microcode and is about 365 * to squash uncommitted instructions to fully drain the pipeline. 366 */ 367 void commitDrained(ThreadID tid); 368 369 /** Switches out this CPU. */ 370 void switchOut() override; 371 372 /** Takes over from another CPU. */ 373 void takeOverFrom(BaseCPU *oldCPU) override; 374 375 void verifyMemoryMode() const override; 376 377 /** Get the current instruction sequence number, and increment it. */ 378 InstSeqNum getAndIncrementInstSeq() 379 { return globalSeqNum++; } 380 381 /** Traps to handle given fault. */ 382 void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst); 383 384 /** HW return from error interrupt. */ 385 Fault hwrei(ThreadID tid); 386 387 bool simPalCheck(int palFunc, ThreadID tid); 388 389 /** Returns the Fault for any valid interrupt. */ 390 Fault getInterrupts(); 391 392 /** Processes any an interrupt fault. */ 393 void processInterrupts(const Fault &interrupt); 394 395 /** Halts the CPU. */ 396 void halt() { panic("Halt not implemented!\n"); } 397 398 /** Register accessors. Index refers to the physical register index. */ 399 400 /** Reads a miscellaneous register. */ 401 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid) const; 402 403 /** Reads a misc. register, including any side effects the read 404 * might have as defined by the architecture. 405 */ 406 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid); 407 408 /** Sets a miscellaneous register. */ 409 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, 410 ThreadID tid); 411 412 /** Sets a misc. register, including any side effects the write 413 * might have as defined by the architecture. 414 */ 415 void setMiscReg(int misc_reg, const TheISA::MiscReg &val, 416 ThreadID tid); 417 418 uint64_t readIntReg(PhysRegIdPtr phys_reg); 419 420 TheISA::FloatReg readFloatReg(PhysRegIdPtr phys_reg); 421 422 TheISA::FloatRegBits readFloatRegBits(PhysRegIdPtr phys_reg); 423
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424 const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const; 425 426 /** 427 * Read physical vector register for modification. 428 */ 429 VecRegContainer& getWritableVecReg(PhysRegIdPtr reg_idx); 430 431 /** 432 * Read physical vector register lane 433 */ 434 template<typename VecElem, int LaneIdx> 435 VecLaneT<VecElem, true> 436 readVecLane(PhysRegIdPtr phys_reg) const 437 { 438 vecRegfileReads++; 439 return regFile.readVecLane<VecElem, LaneIdx>(phys_reg); 440 } 441 442 /** 443 * Read physical vector register lane 444 */ 445 template<typename VecElem> 446 VecLaneT<VecElem, true> 447 readVecLane(PhysRegIdPtr phys_reg) const 448 { 449 vecRegfileReads++; 450 return regFile.readVecLane<VecElem>(phys_reg); 451 } 452 453 /** Write a lane of the destination vector register. */ 454 template<typename LD> 455 void 456 setVecLane(PhysRegIdPtr phys_reg, const LD& val) 457 { 458 vecRegfileWrites++; 459 return regFile.setVecLane(phys_reg, val); 460 } 461 462 const VecElem& readVecElem(PhysRegIdPtr reg_idx) const; 463 |
464 TheISA::CCReg readCCReg(PhysRegIdPtr phys_reg); 465 466 void setIntReg(PhysRegIdPtr phys_reg, uint64_t val); 467 468 void setFloatReg(PhysRegIdPtr phys_reg, TheISA::FloatReg val); 469 470 void setFloatRegBits(PhysRegIdPtr phys_reg, TheISA::FloatRegBits val); 471
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472 void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val); 473 474 void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val); 475 |
476 void setCCReg(PhysRegIdPtr phys_reg, TheISA::CCReg val); 477 478 uint64_t readArchIntReg(int reg_idx, ThreadID tid); 479 480 float readArchFloatReg(int reg_idx, ThreadID tid); 481 482 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); 483
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484 const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const; 485 /** Read architectural vector register for modification. */ 486 VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID tid); 487 488 /** Read architectural vector register lane. */ 489 template<typename VecElem> 490 VecLaneT<VecElem, true> 491 readArchVecLane(int reg_idx, int lId, ThreadID tid) const 492 { 493 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 494 RegId(VecRegClass, reg_idx)); 495 return readVecLane<VecElem>(phys_reg); 496 } 497 498 499 /** Write a lane of the destination vector register. */ 500 template<typename LD> 501 void 502 setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val) 503 { 504 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 505 RegId(VecRegClass, reg_idx)); 506 setVecLane(phys_reg, val); 507 } 508 509 const VecElem& readArchVecElem(const RegIndex& reg_idx, 510 const ElemIndex& ldx, ThreadID tid) const; 511 |
512 TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid); 513 514 /** Architectural register accessors. Looks up in the commit 515 * rename table to obtain the true physical index of the 516 * architected register first, then accesses that physical 517 * register. 518 */ 519 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); 520 521 void setArchFloatReg(int reg_idx, float val, ThreadID tid); 522 523 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); 524
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525 void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid); 526 527 void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, 528 const VecElem& val, ThreadID tid); 529 |
530 void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid); 531 532 /** Sets the commit PC state of a specific thread. */ 533 void pcState(const TheISA::PCState &newPCState, ThreadID tid); 534 535 /** Reads the commit PC state of a specific thread. */ 536 TheISA::PCState pcState(ThreadID tid); 537 538 /** Reads the commit PC of a specific thread. */ 539 Addr instAddr(ThreadID tid); 540 541 /** Reads the commit micro PC of a specific thread. */ 542 MicroPC microPC(ThreadID tid); 543 544 /** Reads the next PC of a specific thread. */ 545 Addr nextInstAddr(ThreadID tid); 546 547 /** Initiates a squash of all in-flight instructions for a given 548 * thread. The source of the squash is an external update of 549 * state through the TC. 550 */ 551 void squashFromTC(ThreadID tid); 552 553 /** Function to add instruction onto the head of the list of the 554 * instructions. Used when new instructions are fetched. 555 */ 556 ListIt addInst(DynInstPtr &inst); 557 558 /** Function to tell the CPU that an instruction has completed. */ 559 void instDone(ThreadID tid, DynInstPtr &inst); 560 561 /** Remove an instruction from the front end of the list. There's 562 * no restriction on location of the instruction. 563 */ 564 void removeFrontInst(DynInstPtr &inst); 565 566 /** Remove all instructions that are not currently in the ROB. 567 * There's also an option to not squash delay slot instructions.*/ 568 void removeInstsNotInROB(ThreadID tid); 569 570 /** Remove all instructions younger than the given sequence number. */ 571 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid); 572 573 /** Removes the instruction pointed to by the iterator. */ 574 inline void squashInstIt(const ListIt &instIt, ThreadID tid); 575 576 /** Cleans up all instructions on the remove list. */ 577 void cleanUpRemovedInsts(); 578 579 /** Debug function to print all instructions on the list. */ 580 void dumpInsts(); 581 582 public: 583#ifndef NDEBUG 584 /** Count of total number of dynamic instructions in flight. */ 585 int instcount; 586#endif 587 588 /** List of all the instructions in flight. */ 589 std::list<DynInstPtr> instList; 590 591 /** List of all the instructions that will be removed at the end of this 592 * cycle. 593 */ 594 std::queue<ListIt> removeList; 595 596#ifdef DEBUG 597 /** Debug structure to keep track of the sequence numbers still in 598 * flight. 599 */ 600 std::set<InstSeqNum> snList; 601#endif 602 603 /** Records if instructions need to be removed this cycle due to 604 * being retired or squashed. 605 */ 606 bool removeInstsThisCycle; 607 608 protected: 609 /** The fetch stage. */ 610 typename CPUPolicy::Fetch fetch; 611 612 /** The decode stage. */ 613 typename CPUPolicy::Decode decode; 614 615 /** The dispatch stage. */ 616 typename CPUPolicy::Rename rename; 617 618 /** The issue/execute/writeback stages. */ 619 typename CPUPolicy::IEW iew; 620 621 /** The commit stage. */ 622 typename CPUPolicy::Commit commit; 623
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624 /** The rename mode of the vector registers */ 625 Enums::VecRegRenameMode vecMode; 626 |
627 /** The register file. */ 628 PhysRegFile regFile; 629 630 /** The free list. */ 631 typename CPUPolicy::FreeList freeList; 632 633 /** The rename map. */ 634 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 635 636 /** The commit rename map. */ 637 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 638 639 /** The re-order buffer. */ 640 typename CPUPolicy::ROB rob; 641 642 /** Active Threads List */ 643 std::list<ThreadID> activeThreads; 644 645 /** Integer Register Scoreboard */ 646 Scoreboard scoreboard; 647 648 std::vector<TheISA::ISA *> isa; 649 650 /** Instruction port. Note that it has to appear after the fetch stage. */ 651 IcachePort icachePort; 652 653 /** Data port. Note that it has to appear after the iew stages */ 654 DcachePort dcachePort; 655 656 public: 657 /** Enum to give each stage a specific index, so when calling 658 * activateStage() or deactivateStage(), they can specify which stage 659 * is being activated/deactivated. 660 */ 661 enum StageIdx { 662 FetchIdx, 663 DecodeIdx, 664 RenameIdx, 665 IEWIdx, 666 CommitIdx, 667 NumStages }; 668 669 /** Typedefs from the Impl to get the structs that each of the 670 * time buffers should use. 671 */ 672 typedef typename CPUPolicy::TimeStruct TimeStruct; 673 674 typedef typename CPUPolicy::FetchStruct FetchStruct; 675 676 typedef typename CPUPolicy::DecodeStruct DecodeStruct; 677 678 typedef typename CPUPolicy::RenameStruct RenameStruct; 679 680 typedef typename CPUPolicy::IEWStruct IEWStruct; 681 682 /** The main time buffer to do backwards communication. */ 683 TimeBuffer<TimeStruct> timeBuffer; 684 685 /** The fetch stage's instruction queue. */ 686 TimeBuffer<FetchStruct> fetchQueue; 687 688 /** The decode stage's instruction queue. */ 689 TimeBuffer<DecodeStruct> decodeQueue; 690 691 /** The rename stage's instruction queue. */ 692 TimeBuffer<RenameStruct> renameQueue; 693 694 /** The IEW stage's instruction queue. */ 695 TimeBuffer<IEWStruct> iewQueue; 696 697 private: 698 /** The activity recorder; used to tell if the CPU has any 699 * activity remaining or if it can go to idle and deschedule 700 * itself. 701 */ 702 ActivityRecorder activityRec; 703 704 public: 705 /** Records that there was time buffer activity this cycle. */ 706 void activityThisCycle() { activityRec.activity(); } 707 708 /** Changes a stage's status to active within the activity recorder. */ 709 void activateStage(const StageIdx idx) 710 { activityRec.activateStage(idx); } 711 712 /** Changes a stage's status to inactive within the activity recorder. */ 713 void deactivateStage(const StageIdx idx) 714 { activityRec.deactivateStage(idx); } 715 716 /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 717 void wakeCPU(); 718 719 virtual void wakeup(ThreadID tid) override; 720 721 /** Gets a free thread id. Use if thread ids change across system. */ 722 ThreadID getFreeTid(); 723 724 public: 725 /** Returns a pointer to a thread context. */ 726 ThreadContext * 727 tcBase(ThreadID tid) 728 { 729 return thread[tid]->getTC(); 730 } 731 732 /** The global sequence number counter. */ 733 InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 734 735 /** Pointer to the checker, which can dynamically verify 736 * instruction results at run time. This can be set to NULL if it 737 * is not being used. 738 */ 739 Checker<Impl> *checker; 740 741 /** Pointer to the system. */ 742 System *system; 743 744 /** Pointers to all of the threads in the CPU. */ 745 std::vector<Thread *> thread; 746 747 /** Threads Scheduled to Enter CPU */ 748 std::list<int> cpuWaitList; 749 750 /** The cycle that the CPU was last running, used for statistics. */ 751 Cycles lastRunningCycle; 752 753 /** The cycle that the CPU was last activated by a new thread*/ 754 Tick lastActivatedCycle; 755 756 /** Mapping for system thread id to cpu id */ 757 std::map<ThreadID, unsigned> threadMap; 758 759 /** Available thread ids in the cpu*/ 760 std::vector<ThreadID> tids; 761 762 /** CPU read function, forwards read to LSQ. */ 763 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 764 int load_idx) 765 { 766 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, load_idx); 767 } 768 769 /** CPU write function, forwards write to LSQ. */ 770 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 771 uint8_t *data, int store_idx) 772 { 773 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh, 774 data, store_idx); 775 } 776 777 /** Used by the fetch unit to get a hold of the instruction port. */ 778 MasterPort &getInstPort() override { return icachePort; } 779 780 /** Get the dcache port (used to find block size for translations). */ 781 MasterPort &getDataPort() override { return dcachePort; } 782 783 /** Stat for total number of times the CPU is descheduled. */ 784 Stats::Scalar timesIdled; 785 /** Stat for total number of cycles the CPU spends descheduled. */ 786 Stats::Scalar idleCycles; 787 /** Stat for total number of cycles the CPU spends descheduled due to a 788 * quiesce operation or waiting for an interrupt. */ 789 Stats::Scalar quiesceCycles; 790 /** Stat for the number of committed instructions per thread. */ 791 Stats::Vector committedInsts; 792 /** Stat for the number of committed ops (including micro ops) per thread. */ 793 Stats::Vector committedOps; 794 /** Stat for the CPI per thread. */ 795 Stats::Formula cpi; 796 /** Stat for the total CPI. */ 797 Stats::Formula totalCpi; 798 /** Stat for the IPC per thread. */ 799 Stats::Formula ipc; 800 /** Stat for the total IPC. */ 801 Stats::Formula totalIpc; 802 803 //number of integer register file accesses 804 Stats::Scalar intRegfileReads; 805 Stats::Scalar intRegfileWrites; 806 //number of float register file accesses 807 Stats::Scalar fpRegfileReads; 808 Stats::Scalar fpRegfileWrites;
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809 //number of vector register file accesses 810 mutable Stats::Scalar vecRegfileReads; 811 Stats::Scalar vecRegfileWrites; |
812 //number of CC register file accesses 813 Stats::Scalar ccRegfileReads; 814 Stats::Scalar ccRegfileWrites; 815 //number of misc 816 Stats::Scalar miscRegfileReads; 817 Stats::Scalar miscRegfileWrites; 818}; 819 820#endif // __CPU_O3_CPU_HH__
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