1/* |
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * Copyright (c) 2011 Regents of the University of California 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; --- 52 unchanged lines hidden (view full) --- 62class ThreadContext; 63template <class> 64class O3ThreadContext; 65 66class Checkpoint; 67class MemObject; 68class Process; 69 |
70class BaseCPUParams; |
71 72class BaseO3CPU : public BaseCPU 73{ 74 //Stuff that's pretty ISA independent will go here. 75 public: 76 BaseO3CPU(BaseCPUParams *params); 77 78 void regStats(); --- 34 unchanged lines hidden (view full) --- 113 114 /** Overall CPU status. */ 115 Status _status; 116 117 /** Per-thread status in CPU, used for SMT. */ 118 Status _threadStatus[Impl::MaxThreads]; 119 120 private: |
121 class TickEvent : public Event 122 { 123 private: 124 /** Pointer to the CPU. */ 125 FullO3CPU<Impl> *cpu; 126 127 public: 128 /** Constructs a tick event. */ --- 193 unchanged lines hidden (view full) --- 322 void activateContext(ThreadID tid, int delay); 323 324 /** Remove Thread from Active Threads List */ 325 void suspendContext(ThreadID tid); 326 327 /** Remove Thread from Active Threads List && 328 * Possibly Remove Thread Context from CPU. 329 */ |
330 bool deallocateContext(ThreadID tid, bool remove, int delay = 1); |
331 332 /** Remove Thread from Active Threads List && 333 * Remove Thread Context from CPU. 334 */ 335 void haltContext(ThreadID tid); 336 337 /** Activate a Thread When CPU Resources are Available. */ 338 void activateWhenReady(ThreadID tid); --- 6 unchanged lines hidden (view full) --- 345 346 /** Serialize state. */ 347 virtual void serialize(std::ostream &os); 348 349 /** Unserialize from a checkpoint. */ 350 virtual void unserialize(Checkpoint *cp, const std::string §ion); 351 352 public: |
353 /** Executes a syscall. 354 * @todo: Determine if this needs to be virtual. 355 */ 356 void syscall(int64_t callnum, ThreadID tid); |
357 358 /** Starts draining the CPU's pipeline of all instructions in 359 * order to stop all memory accesses. */ 360 virtual unsigned int drain(Event *drain_event); 361 362 /** Resumes execution after a drain. */ 363 virtual void resume(); 364 --- 23 unchanged lines hidden (view full) --- 388 Fault getInterrupts(); 389 390 /** Processes any an interrupt fault. */ 391 void processInterrupts(Fault interrupt); 392 393 /** Halts the CPU. */ 394 void halt() { panic("Halt not implemented!\n"); } 395 |
396 /** Update the Virt and Phys ports of all ThreadContexts to 397 * reflect change in memory connections. */ 398 void updateMemPorts(); 399 |
400 /** Check if this address is a valid instruction address. */ 401 bool validInstAddr(Addr addr) { return true; } 402 403 /** Check if this address is a valid data address. */ 404 bool validDataAddr(Addr addr) { return true; } 405#endif 406 407 /** Register accessors. Index refers to the physical register index. */ --- 155 unchanged lines hidden (view full) --- 563 /** Active Threads List */ 564 std::list<ThreadID> activeThreads; 565 566 /** Integer Register Scoreboard */ 567 Scoreboard scoreboard; 568 569 TheISA::ISA isa[Impl::MaxThreads]; 570 |
571 public: 572 /** Enum to give each stage a specific index, so when calling 573 * activateStage() or deactivateStage(), they can specify which stage 574 * is being activated/deactivated. 575 */ 576 enum StageIdx { 577 FetchIdx, 578 DecodeIdx, --- 70 unchanged lines hidden (view full) --- 649 /** The global sequence number counter. */ 650 InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 651 652#if USE_CHECKER 653 /** Pointer to the checker, which can dynamically verify 654 * instruction results at run time. This can be set to NULL if it 655 * is not being used. 656 */ |
657 Checker<DynInstPtr> *checker; |
658#endif 659 660 /** Pointer to the system. */ 661 System *system; 662 663 /** Event to call process() on once draining has completed. */ 664 Event *drainEvent; 665 --- 35 unchanged lines hidden (view full) --- 701 /** CPU write function, forwards write to LSQ. */ 702 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 703 uint8_t *data, int store_idx) 704 { 705 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh, 706 data, store_idx); 707 } 708 |
709 /** Get the dcache port (used to find block size for translations). */ |
710 Port *getDcachePort() { return this->iew.ldstQueue.getDcachePort(); } |
711 712 Addr lockAddr; 713 714 /** Temporary fix for the lock flag, works in the UP case. */ 715 bool lockFlag; 716 717 /** Stat for total number of times the CPU is descheduled. */ 718 Stats::Scalar timesIdled; 719 /** Stat for total number of cycles the CPU spends descheduled. */ 720 Stats::Scalar idleCycles; |
721 /** Stat for the number of committed instructions per thread. */ 722 Stats::Vector committedInsts; 723 /** Stat for the total number of committed instructions. */ 724 Stats::Scalar totalCommittedInsts; 725 /** Stat for the CPI per thread. */ 726 Stats::Formula cpi; 727 /** Stat for the total CPI. */ 728 Stats::Formula totalCpi; --- 17 unchanged lines hidden --- |