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< * Copyright (c) 2011 ARM Limited
< * All rights reserved
< *
< * The license below extends only to copyright in the software and shall
< * not be construed as granting a license to any other intellectual
< * property including but not limited to intellectual property relating
< * to a hardware implementation of the functionality of the software
< * licensed hereunder. You may use the software subject to the license
< * terms below provided that you ensure that this notice is replicated
< * unmodified and in its entirety in all distributions of the software,
< * modified or unmodified, in source code or in binary form.
< *
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< struct BaseCPUParams;
---
> class BaseCPUParams;
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<
< /**
< * IcachePort class for instruction fetch.
< */
< class IcachePort : public CpuPort
< {
< protected:
< /** Pointer to fetch. */
< DefaultFetch<Impl> *fetch;
<
< public:
< /** Default constructor. */
< IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
< : CpuPort(_fetch->name() + "-iport", _cpu), fetch(_fetch)
< { }
<
< protected:
<
< /** Timing version of receive. Handles setting fetch to the
< * proper status to start fetching. */
< virtual bool recvTiming(PacketPtr pkt);
<
< /** Handles doing a retry of a failed fetch. */
< virtual void recvRetry();
< };
<
< /**
< * DcachePort class for the load/store queue.
< */
< class DcachePort : public CpuPort
< {
< protected:
<
< /** Pointer to LSQ. */
< LSQ<Impl> *lsq;
<
< public:
< /** Default constructor. */
< DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
< : CpuPort(_lsq->name() + "-dport", _cpu), lsq(_lsq)
< { }
<
< protected:
<
< /** Timing version of receive. Handles writing back and
< * completing the load or store that has returned from
< * memory. */
< virtual bool recvTiming(PacketPtr pkt);
<
< /** Handles doing a retry of the previous send. */
< virtual void recvRetry();
<
< /**
< * As this CPU requires snooping to maintain the load store queue
< * change the behaviour from the base CPU port.
< *
< * @return true since we have to snoop
< */
< virtual bool isSnooping()
< { return true; }
< };
<
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< bool scheduleDeallocateContext(ThreadID tid, bool remove, int delay = 1);
---
> bool deallocateContext(ThreadID tid, bool remove, int delay = 1);
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< #if !FULL_SYSTEM
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< #endif
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> /** Update the Virt and Phys ports of all ThreadContexts to
> * reflect change in memory connections. */
> void updateMemPorts();
>
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< /** Instruction port. Note that it has to appear after the fetch stage. */
< IcachePort icachePort;
<
< /** Data port. Note that it has to appear after the iew stages */
< DcachePort dcachePort;
<
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< Checker<Impl> *checker;
---
> Checker<DynInstPtr> *checker;
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< /** Used by the fetch unit to get a hold of the instruction port. */
< Port* getIcachePort() { return &icachePort; }
<
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< Port* getDcachePort() { return &dcachePort; }
---
> Port *getDcachePort() { return this->iew.ldstQueue.getDcachePort(); }
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< /** Stat for total number of cycles the CPU spends descheduled due to a
< * quiesce operation or waiting for an interrupt. */
< Stats::Scalar quiesceCycles;