101a102
> typedef O3ThreadState<Impl> ImplState;
203a205,211
> #if !FULL_SYSTEM
> TheISA::IntReg getSyscallArg(int i, int tid);
>
> /** Used to shift args for indirect syscall. */
> void setSyscallArg(int i, TheISA::IntReg val, int tid);
> #endif
>
260c268
< FullO3CPU(O3CPU *o3_cpu, DerivO3CPUParams *params);
---
> FullO3CPU(DerivO3CPUParams *params);
265c273
< void fullCPURegStats();
---
> void regStats();
371,374c379,381
< /** Executes a syscall on this cycle.
< * ---------------------------------------
< * Note: this is a virtual function. CPU-Specific
< * functionality defined in derived classes
---
> #if !FULL_SYSTEM
> /** Executes a syscall.
> * @todo: Determine if this needs to be virtual.
376c383
< virtual void syscall(int tid) { panic("Unimplemented!"); }
---
> void syscall(int64_t callnum, int tid);
377a385,389
> /** Sets the return value of a syscall. */
> void setSyscallReturn(SyscallReturn return_value, int tid);
>
> #endif
>
397a410,412
> /** Traps to handle given fault. */
> void trap(Fault fault, unsigned tid);
>
398a414,430
> /** Posts an interrupt. */
> void post_interrupt(int int_num, int index);
>
> /** HW return from error interrupt. */
> Fault hwrei(unsigned tid);
>
> bool simPalCheck(int palFunc, unsigned tid);
>
> /** Returns the Fault for any valid interrupt. */
> Fault getInterrupts();
>
> /** Processes any an interrupt fault. */
> void processInterrupts(Fault interrupt);
>
> /** Halts the CPU. */
> void halt() { panic("Halt not implemented!\n"); }
>
427a460,477
>
> /** Reads a miscellaneous register. */
> TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid);
>
> /** Reads a misc. register, including any side effects the read
> * might have as defined by the architecture.
> */
> TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
>
> /** Sets a miscellaneous register. */
> void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
>
> /** Sets a misc. register, including any side effects the write
> * might have as defined by the architecture.
> */
> void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
> unsigned tid);
>
498a549,554
> /** Initiates a squash of all in-flight instructions for a given
> * thread. The source of the squash is an external update of
> * state through the TC.
> */
> void squashFromTC(unsigned tid);
>
713a770,788
> /** CPU read function, forwards read to LSQ. */
> template <class T>
> Fault read(RequestPtr &req, T &data, int load_idx)
> {
> return this->iew.ldstQueue.read(req, data, load_idx);
> }
>
> /** CPU write function, forwards write to LSQ. */
> template <class T>
> Fault write(RequestPtr &req, T &data, int store_idx)
> {
> return this->iew.ldstQueue.write(req, data, store_idx);
> }
>
> Addr lockAddr;
>
> /** Temporary fix for the lock flag, works in the UP case. */
> bool lockFlag;
>