26a27,28
> *
> * Authors: Kevin Lim
29,30c31,36
< #ifndef __CPU_O3_CPU_HH__
< #define __CPU_O3_CPU_HH__
---
> //Todo: Add in a lot of the functions that are ISA specific. Also define
> //the functions that currently exist within the base cpu class. Define
> //everything for the simobject stuff so it can be serialized and
> //instantiated, add in debugging statements everywhere. Have CPU schedule
> //itself properly. Threads!
> // Avoid running stages and advancing queues if idle/stalled.
31a38,40
> #ifndef __CPU_O3_CPU_FULL_CPU_HH__
> #define __CPU_O3_CPU_FULL_CPU_HH__
>
34,35d42
< #include <queue>
< #include <set>
41d47
< #include "cpu/activity.hh"
46,47d51
< #include "cpu/o3/scoreboard.hh"
< #include "cpu/o3/thread_state.hh"
50,51d53
< template <class>
< class Checker;
53c55
< class MemInterface;
---
> class FunctionalMemory;
62c64,68
< BaseFullCPU(Params *params);
---
> #if FULL_SYSTEM
> BaseFullCPU(Params ¶ms);
> #else
> BaseFullCPU(Params ¶ms);
> #endif // FULL_SYSTEM
64,65d69
< void regStats();
<
74c78
< // Typedefs from the Impl here.
---
> //Put typedefs from the Impl here.
79,82d82
< typedef O3ThreadState<Impl> Thread;
<
< typedef typename std::list<DynInstPtr>::iterator ListIt;
<
88,89c88
< Blocked,
< SwitchedOut
---
> Blocked // ?
92d90
< /** Overall CPU status. */
99d96
< /** Pointer to the CPU. */
103d99
< /** Constructs a tick event. */
105,106d100
<
< /** Processes a tick event, calling tick() on the CPU. */
108d101
< /** Returns the description of the tick event. */
112d104
< /** The tick event used for scheduling CPU ticks. */
115c107
< /** Schedule tick event, regardless of its current state. */
---
> /// Schedule tick event, regardless of its current state.
119c111
< tickEvent.reschedule(curTick + cycles(delay));
---
> tickEvent.reschedule(curTick + delay);
121c113
< tickEvent.schedule(curTick + cycles(delay));
---
> tickEvent.schedule(curTick + delay);
124c116
< /** Unschedule tick event, regardless of its current state. */
---
> /// Unschedule tick event, regardless of its current state.
132,134c124
< /** Constructs a CPU with the given parameters. */
< FullO3CPU(Params *params);
< /** Destructor. */
---
> FullO3CPU(Params ¶ms);
137d126
< /** Registers statistics. */
140,142d128
< /** Ticks CPU, calling tick() on each stage, and checking the overall
< * activity to see if the CPU should deschedule itself.
< */
145d130
< /** Initialize the CPU */
148,149c133,136
< /** Setup CPU to insert a thread's context */
< void insertThread(unsigned tid);
---
> void activateContext(int thread_num, int delay);
> void suspendContext(int thread_num);
> void deallocateContext(int thread_num);
> void haltContext(int thread_num);
151,207c138
< /** Remove all of a thread's context from CPU */
< void removeThread(unsigned tid);
<
< /** Count the Total Instructions Committed in the CPU. */
< virtual Counter totalInstructions() const
< {
< Counter total(0);
<
< for (int i=0; i < thread.size(); i++)
< total += thread[i]->numInst;
<
< return total;
< }
<
< /** Add Thread to Active Threads List. */
< void activateContext(int tid, int delay);
<
< /** Remove Thread from Active Threads List */
< void suspendContext(int tid);
<
< /** Remove Thread from Active Threads List &&
< * Remove Thread Context from CPU.
< */
< void deallocateContext(int tid);
<
< /** Remove Thread from Active Threads List &&
< * Remove Thread Context from CPU.
< */
< void haltContext(int tid);
<
< /** Activate a Thread When CPU Resources are Available. */
< void activateWhenReady(int tid);
<
< /** Add or Remove a Thread Context in the CPU. */
< void doContextSwitch();
<
< /** Update The Order In Which We Process Threads. */
< void updateThreadPriority();
<
< /** Executes a syscall on this cycle.
< * ---------------------------------------
< * Note: this is a virtual function. CPU-Specific
< * functionality defined in derived classes
< */
< virtual void syscall(int tid) { panic("Unimplemented!"); }
<
< /** Check if there are any system calls pending. */
< void checkSyscalls();
<
< /** Switches out this CPU.
< */
< void switchOut(Sampler *sampler);
<
< void signalSwitched();
<
< /** Takes over from another CPU.
< */
---
> void switchOut();
211,212c142
< InstSeqNum getAndIncrementInstSeq()
< { return globalSeqNum++; }
---
> InstSeqNum getAndIncrementInstSeq();
222,223c152,153
< int getInstAsid(unsigned tid)
< { return regFile.miscRegs[tid].getInstAsid(); }
---
> int getInstAsid()
> { return regFile.miscRegs.getInstAsid(); }
226,227c156,157
< int getDataAsid(unsigned tid)
< { return regFile.miscRegs[tid].getDataAsid(); }
---
> int getDataAsid()
> { return regFile.miscRegs.getDataAsid(); }
229,231c159,160
< /** Check if this address is a valid instruction address. */
< bool validInstAddr(Addr addr,unsigned tid)
< { return thread[tid]->validInstAddr(addr); }
---
> bool validInstAddr(Addr addr)
> { return thread[0]->validInstAddr(addr); }
233,235c162,163
< /** Check if this address is a valid data address. */
< bool validDataAddr(Addr addr,unsigned tid)
< { return thread[tid]->validDataAddr(addr); }
---
> bool validDataAddr(Addr addr)
> { return thread[0]->validDataAddr(addr); }
237,239c165,166
< /** Get instruction asid. */
< int getInstAsid(unsigned tid)
< { return thread[tid]->asid; }
---
> int getInstAsid() { return thread[0]->getInstAsid(); }
> int getDataAsid() { return thread[0]->getDataAsid(); }
241,244d167
< /** Get data asid. */
< int getDataAsid(unsigned tid)
< { return thread[tid]->asid; }
<
270c193
< uint64_t readArchIntReg(int reg_idx, unsigned tid);
---
> uint64_t readPC();
272c195
< float readArchFloatRegSingle(int reg_idx, unsigned tid);
---
> void setNextPC(uint64_t val);
274c197
< double readArchFloatRegDouble(int reg_idx, unsigned tid);
---
> void setPC(Addr new_PC);
276,293d198
< uint64_t readArchFloatRegInt(int reg_idx, unsigned tid);
<
< void setArchIntReg(int reg_idx, uint64_t val, unsigned tid);
<
< void setArchFloatRegSingle(int reg_idx, float val, unsigned tid);
<
< void setArchFloatRegDouble(int reg_idx, double val, unsigned tid);
<
< void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid);
<
< uint64_t readPC(unsigned tid);
<
< void setPC(Addr new_PC,unsigned tid);
<
< uint64_t readNextPC(unsigned tid);
<
< void setNextPC(uint64_t val,unsigned tid);
<
297c202
< ListIt addInst(DynInstPtr &inst);
---
> void addInst(DynInstPtr &inst);
300c205
< void instDone(unsigned tid);
---
> void instDone();
302,303c207,215
< /** Add Instructions to the CPU Remove List*/
< void addToRemoveList(DynInstPtr &inst);
---
> /** Remove all instructions in back of the given instruction, but leave
> * that instruction in the list. This is useful in a squash, when there
> * are instructions in this list that don't exist in structures such as
> * the ROB. The instruction doesn't have to be the last instruction in
> * the list, but will be once this function completes.
> * @todo: Remove only up until that inst? Squashed inst is most likely
> * valid.
> */
> void removeBackInst(DynInstPtr &inst);
305,306c217,222
< /** Remove an instruction from the front end of the list. There's
< * no restriction on location of the instruction.
---
> /** Remove an instruction from the front of the list. It is expected
> * that there are no instructions in front of it (that is, none are older
> * than the instruction being removed). Used when retiring instructions.
> * @todo: Remove the argument to this function, and just have it remove
> * last instruction once it's verified that commit has the same ordering
> * as the instruction list.
311c227
< void removeInstsNotInROB(unsigned tid);
---
> void removeInstsNotInROB();
314c230
< void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
---
> void removeInstsUntil(const InstSeqNum &seq_num);
316,319d231
< inline void squashInstIt(const ListIt &instIt, const unsigned &tid);
<
< void cleanUpRemovedInsts();
<
321c233
< // void removeAllInsts();
---
> void removeAllInsts();
326,327c238,239
< * commit can tell the instruction queue that they have
< * completed. Eventually this hack should be removed.
---
> * commit can tell the instruction queue that they have completed.
> * Eventually this hack should be removed.
329c241
< // void wakeDependents(DynInstPtr &inst);
---
> void wakeDependents(DynInstPtr &inst);
333c245
< std::list<DynInstPtr> instList;
---
> list<DynInstPtr> instList;
335,348c247
< /** List of all the instructions that will be removed at the end of this
< * cycle.
< */
< std::queue<ListIt> removeList;
<
< #ifdef DEBUG
< std::set<InstSeqNum> snList;
< #endif
<
< /** Records if instructions need to be removed this cycle due to
< * being retired or squashed.
< */
< bool removeInstsThisCycle;
<
---
> //not sure these should be private.
352a252,254
> /** The fetch stage's status. */
> typename CPUPolicy::Fetch::Status fetchStatus;
>
355a258,260
> /** The decode stage's status. */
> typename CPUPolicy::Decode::Status decodeStatus;
>
358a264,266
> /** The dispatch stage's status. */
> typename CPUPolicy::Rename::Status renameStatus;
>
361a270,272
> /** The issue/execute/writeback stage's status. */
> typename CPUPolicy::IEW::Status iewStatus;
>
364a276,281
> /** The fetch stage's status. */
> typename CPUPolicy::Commit::Status commitStatus;
>
> //Might want to just pass these objects in to the constructors of the
> //appropriate stage. regFile is in iew, freeList in dispatch, renameMap
> //in dispatch, and the rob in commit.
372c289
< typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
---
> typename CPUPolicy::RenameMap renameMap;
374,376d290
< /** The commit rename map. */
< typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
<
380,385d293
< /** Active Threads List */
< std::list<unsigned> activeThreads;
<
< /** Integer Register Scoreboard */
< Scoreboard scoreboard;
<
387,398d294
< /** Enum to give each stage a specific index, so when calling
< * activateStage() or deactivateStage(), they can specify which stage
< * is being activated/deactivated.
< */
< enum StageIdx {
< FetchIdx,
< DecodeIdx,
< RenameIdx,
< IEWIdx,
< CommitIdx,
< NumStages };
<
428c324,325
< ActivityRecorder activityRec;
---
> /** The temporary exec context to support older accessors. */
> CPUExecContext *cpuXC;
430,444d326
< void activityThisCycle() { activityRec.activity(); }
<
< void activateStage(const StageIdx idx)
< { activityRec.activateStage(idx); }
<
< void deactivateStage(const StageIdx idx)
< { activityRec.deactivateStage(idx); }
<
< /** Wakes the CPU, rescheduling the CPU if it's not already active. */
< void wakeCPU();
<
< /** Gets a free thread id. Use if thread ids change across system. */
< int getFreeTid();
<
< public:
446c328
< ExecContext *xcBase(unsigned tid)
---
> ExecContext *xcBase()
448c330
< return thread[tid]->getXCProxy();
---
> return thread[0]->getProxy();
451c333,337
< /** The global sequence number counter. */
---
> CPUExecContext *cpuXCBase()
> {
> return thread[0];
> }
>
454,455d339
< Checker<DynInstPtr> *checker;
<
457d340
< /** Pointer to the system. */
460d342
< /** Pointer to the memory controller. */
462d343
< /** Pointer to physical memory. */
464d344
< #endif
466,467c346,347
< /** Pointer to memory. */
< FunctionalMemory *mem;
---
> AlphaITB *itb;
> AlphaDTB *dtb;
469,478c349
< Sampler *sampler;
<
< int switchCount;
<
< // List of all ExecContexts.
< std::vector<Thread *> thread;
<
< #if 0
< /** Page table pointer. */
< PageTable *pTable;
---
> // SWContext *swCtx;
479a351
> std::vector<CPUExecContext *> thread;
481c353,354
< /** Pointer to the icache interface. */
---
> FunctionalMemory *mem;
>
483d355
< /** Pointer to the dcache interface. */
486d357
< /** Whether or not the CPU should defer its registration. */
489,490c360
< /** Is there a context switch pending? */
< bool contextSwitch;
---
> Counter numInsts;
492,522c362
< /** Threads Scheduled to Enter CPU */
< std::list<int> cpuWaitList;
<
< /** The cycle that the CPU was last running, used for statistics. */
< Tick lastRunningCycle;
<
< /** Number of Threads CPU can process */
< unsigned numThreads;
<
< /** Mapping for system thread id to cpu id */
< std::map<unsigned,unsigned> threadMap;
<
< /** Available thread ids in the cpu*/
< std::vector<unsigned> tids;
<
< /** Stat for total number of times the CPU is descheduled. */
< Stats::Scalar<> timesIdled;
< /** Stat for total number of cycles the CPU spends descheduled. */
< Stats::Scalar<> idleCycles;
< /** Stat for the number of committed instructions per thread. */
< Stats::Vector<> committedInsts;
< /** Stat for the total number of committed instructions. */
< Stats::Scalar<> totalCommittedInsts;
< /** Stat for the CPI per thread. */
< Stats::Formula cpi;
< /** Stat for the total CPI. */
< Stats::Formula totalCpi;
< /** Stat for the IPC per thread. */
< Stats::Formula ipc;
< /** Stat for the total IPC. */
< Stats::Formula totalIpc;
---
> Counter funcExeInst;
525c365
< #endif // __CPU_O3_CPU_HH__
---
> #endif
> *
> * Authors: Kevin Lim
29,30c31,36
< #ifndef __CPU_O3_CPU_HH__
< #define __CPU_O3_CPU_HH__
---
> //Todo: Add in a lot of the functions that are ISA specific. Also define
> //the functions that currently exist within the base cpu class. Define
> //everything for the simobject stuff so it can be serialized and
> //instantiated, add in debugging statements everywhere. Have CPU schedule
> //itself properly. Threads!
> // Avoid running stages and advancing queues if idle/stalled.
31a38,40
> #ifndef __CPU_O3_CPU_FULL_CPU_HH__
> #define __CPU_O3_CPU_FULL_CPU_HH__
>
34,35d42
< #include <queue>
< #include <set>
41d47
< #include "cpu/activity.hh"
46,47d51
< #include "cpu/o3/scoreboard.hh"
< #include "cpu/o3/thread_state.hh"
50,51d53
< template <class>
< class Checker;
53c55
< class MemInterface;
---
> class FunctionalMemory;
62c64,68
< BaseFullCPU(Params *params);
---
> #if FULL_SYSTEM
> BaseFullCPU(Params ¶ms);
> #else
> BaseFullCPU(Params ¶ms);
> #endif // FULL_SYSTEM
64,65d69
< void regStats();
<
74c78
< // Typedefs from the Impl here.
---
> //Put typedefs from the Impl here.
79,82d82
< typedef O3ThreadState<Impl> Thread;
<
< typedef typename std::list<DynInstPtr>::iterator ListIt;
<
88,89c88
< Blocked,
< SwitchedOut
---
> Blocked // ?
92d90
< /** Overall CPU status. */
99d96
< /** Pointer to the CPU. */
103d99
< /** Constructs a tick event. */
105,106d100
<
< /** Processes a tick event, calling tick() on the CPU. */
108d101
< /** Returns the description of the tick event. */
112d104
< /** The tick event used for scheduling CPU ticks. */
115c107
< /** Schedule tick event, regardless of its current state. */
---
> /// Schedule tick event, regardless of its current state.
119c111
< tickEvent.reschedule(curTick + cycles(delay));
---
> tickEvent.reschedule(curTick + delay);
121c113
< tickEvent.schedule(curTick + cycles(delay));
---
> tickEvent.schedule(curTick + delay);
124c116
< /** Unschedule tick event, regardless of its current state. */
---
> /// Unschedule tick event, regardless of its current state.
132,134c124
< /** Constructs a CPU with the given parameters. */
< FullO3CPU(Params *params);
< /** Destructor. */
---
> FullO3CPU(Params ¶ms);
137d126
< /** Registers statistics. */
140,142d128
< /** Ticks CPU, calling tick() on each stage, and checking the overall
< * activity to see if the CPU should deschedule itself.
< */
145d130
< /** Initialize the CPU */
148,149c133,136
< /** Setup CPU to insert a thread's context */
< void insertThread(unsigned tid);
---
> void activateContext(int thread_num, int delay);
> void suspendContext(int thread_num);
> void deallocateContext(int thread_num);
> void haltContext(int thread_num);
151,207c138
< /** Remove all of a thread's context from CPU */
< void removeThread(unsigned tid);
<
< /** Count the Total Instructions Committed in the CPU. */
< virtual Counter totalInstructions() const
< {
< Counter total(0);
<
< for (int i=0; i < thread.size(); i++)
< total += thread[i]->numInst;
<
< return total;
< }
<
< /** Add Thread to Active Threads List. */
< void activateContext(int tid, int delay);
<
< /** Remove Thread from Active Threads List */
< void suspendContext(int tid);
<
< /** Remove Thread from Active Threads List &&
< * Remove Thread Context from CPU.
< */
< void deallocateContext(int tid);
<
< /** Remove Thread from Active Threads List &&
< * Remove Thread Context from CPU.
< */
< void haltContext(int tid);
<
< /** Activate a Thread When CPU Resources are Available. */
< void activateWhenReady(int tid);
<
< /** Add or Remove a Thread Context in the CPU. */
< void doContextSwitch();
<
< /** Update The Order In Which We Process Threads. */
< void updateThreadPriority();
<
< /** Executes a syscall on this cycle.
< * ---------------------------------------
< * Note: this is a virtual function. CPU-Specific
< * functionality defined in derived classes
< */
< virtual void syscall(int tid) { panic("Unimplemented!"); }
<
< /** Check if there are any system calls pending. */
< void checkSyscalls();
<
< /** Switches out this CPU.
< */
< void switchOut(Sampler *sampler);
<
< void signalSwitched();
<
< /** Takes over from another CPU.
< */
---
> void switchOut();
211,212c142
< InstSeqNum getAndIncrementInstSeq()
< { return globalSeqNum++; }
---
> InstSeqNum getAndIncrementInstSeq();
222,223c152,153
< int getInstAsid(unsigned tid)
< { return regFile.miscRegs[tid].getInstAsid(); }
---
> int getInstAsid()
> { return regFile.miscRegs.getInstAsid(); }
226,227c156,157
< int getDataAsid(unsigned tid)
< { return regFile.miscRegs[tid].getDataAsid(); }
---
> int getDataAsid()
> { return regFile.miscRegs.getDataAsid(); }
229,231c159,160
< /** Check if this address is a valid instruction address. */
< bool validInstAddr(Addr addr,unsigned tid)
< { return thread[tid]->validInstAddr(addr); }
---
> bool validInstAddr(Addr addr)
> { return thread[0]->validInstAddr(addr); }
233,235c162,163
< /** Check if this address is a valid data address. */
< bool validDataAddr(Addr addr,unsigned tid)
< { return thread[tid]->validDataAddr(addr); }
---
> bool validDataAddr(Addr addr)
> { return thread[0]->validDataAddr(addr); }
237,239c165,166
< /** Get instruction asid. */
< int getInstAsid(unsigned tid)
< { return thread[tid]->asid; }
---
> int getInstAsid() { return thread[0]->getInstAsid(); }
> int getDataAsid() { return thread[0]->getDataAsid(); }
241,244d167
< /** Get data asid. */
< int getDataAsid(unsigned tid)
< { return thread[tid]->asid; }
<
270c193
< uint64_t readArchIntReg(int reg_idx, unsigned tid);
---
> uint64_t readPC();
272c195
< float readArchFloatRegSingle(int reg_idx, unsigned tid);
---
> void setNextPC(uint64_t val);
274c197
< double readArchFloatRegDouble(int reg_idx, unsigned tid);
---
> void setPC(Addr new_PC);
276,293d198
< uint64_t readArchFloatRegInt(int reg_idx, unsigned tid);
<
< void setArchIntReg(int reg_idx, uint64_t val, unsigned tid);
<
< void setArchFloatRegSingle(int reg_idx, float val, unsigned tid);
<
< void setArchFloatRegDouble(int reg_idx, double val, unsigned tid);
<
< void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid);
<
< uint64_t readPC(unsigned tid);
<
< void setPC(Addr new_PC,unsigned tid);
<
< uint64_t readNextPC(unsigned tid);
<
< void setNextPC(uint64_t val,unsigned tid);
<
297c202
< ListIt addInst(DynInstPtr &inst);
---
> void addInst(DynInstPtr &inst);
300c205
< void instDone(unsigned tid);
---
> void instDone();
302,303c207,215
< /** Add Instructions to the CPU Remove List*/
< void addToRemoveList(DynInstPtr &inst);
---
> /** Remove all instructions in back of the given instruction, but leave
> * that instruction in the list. This is useful in a squash, when there
> * are instructions in this list that don't exist in structures such as
> * the ROB. The instruction doesn't have to be the last instruction in
> * the list, but will be once this function completes.
> * @todo: Remove only up until that inst? Squashed inst is most likely
> * valid.
> */
> void removeBackInst(DynInstPtr &inst);
305,306c217,222
< /** Remove an instruction from the front end of the list. There's
< * no restriction on location of the instruction.
---
> /** Remove an instruction from the front of the list. It is expected
> * that there are no instructions in front of it (that is, none are older
> * than the instruction being removed). Used when retiring instructions.
> * @todo: Remove the argument to this function, and just have it remove
> * last instruction once it's verified that commit has the same ordering
> * as the instruction list.
311c227
< void removeInstsNotInROB(unsigned tid);
---
> void removeInstsNotInROB();
314c230
< void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
---
> void removeInstsUntil(const InstSeqNum &seq_num);
316,319d231
< inline void squashInstIt(const ListIt &instIt, const unsigned &tid);
<
< void cleanUpRemovedInsts();
<
321c233
< // void removeAllInsts();
---
> void removeAllInsts();
326,327c238,239
< * commit can tell the instruction queue that they have
< * completed. Eventually this hack should be removed.
---
> * commit can tell the instruction queue that they have completed.
> * Eventually this hack should be removed.
329c241
< // void wakeDependents(DynInstPtr &inst);
---
> void wakeDependents(DynInstPtr &inst);
333c245
< std::list<DynInstPtr> instList;
---
> list<DynInstPtr> instList;
335,348c247
< /** List of all the instructions that will be removed at the end of this
< * cycle.
< */
< std::queue<ListIt> removeList;
<
< #ifdef DEBUG
< std::set<InstSeqNum> snList;
< #endif
<
< /** Records if instructions need to be removed this cycle due to
< * being retired or squashed.
< */
< bool removeInstsThisCycle;
<
---
> //not sure these should be private.
352a252,254
> /** The fetch stage's status. */
> typename CPUPolicy::Fetch::Status fetchStatus;
>
355a258,260
> /** The decode stage's status. */
> typename CPUPolicy::Decode::Status decodeStatus;
>
358a264,266
> /** The dispatch stage's status. */
> typename CPUPolicy::Rename::Status renameStatus;
>
361a270,272
> /** The issue/execute/writeback stage's status. */
> typename CPUPolicy::IEW::Status iewStatus;
>
364a276,281
> /** The fetch stage's status. */
> typename CPUPolicy::Commit::Status commitStatus;
>
> //Might want to just pass these objects in to the constructors of the
> //appropriate stage. regFile is in iew, freeList in dispatch, renameMap
> //in dispatch, and the rob in commit.
372c289
< typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
---
> typename CPUPolicy::RenameMap renameMap;
374,376d290
< /** The commit rename map. */
< typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
<
380,385d293
< /** Active Threads List */
< std::list<unsigned> activeThreads;
<
< /** Integer Register Scoreboard */
< Scoreboard scoreboard;
<
387,398d294
< /** Enum to give each stage a specific index, so when calling
< * activateStage() or deactivateStage(), they can specify which stage
< * is being activated/deactivated.
< */
< enum StageIdx {
< FetchIdx,
< DecodeIdx,
< RenameIdx,
< IEWIdx,
< CommitIdx,
< NumStages };
<
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< ActivityRecorder activityRec;
---
> /** The temporary exec context to support older accessors. */
> CPUExecContext *cpuXC;
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< void activityThisCycle() { activityRec.activity(); }
<
< void activateStage(const StageIdx idx)
< { activityRec.activateStage(idx); }
<
< void deactivateStage(const StageIdx idx)
< { activityRec.deactivateStage(idx); }
<
< /** Wakes the CPU, rescheduling the CPU if it's not already active. */
< void wakeCPU();
<
< /** Gets a free thread id. Use if thread ids change across system. */
< int getFreeTid();
<
< public:
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< ExecContext *xcBase(unsigned tid)
---
> ExecContext *xcBase()
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< return thread[tid]->getXCProxy();
---
> return thread[0]->getProxy();
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< /** The global sequence number counter. */
---
> CPUExecContext *cpuXCBase()
> {
> return thread[0];
> }
>
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< Checker<DynInstPtr> *checker;
<
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< /** Pointer to the system. */
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< /** Pointer to the memory controller. */
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< /** Pointer to physical memory. */
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< #endif
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< /** Pointer to memory. */
< FunctionalMemory *mem;
---
> AlphaITB *itb;
> AlphaDTB *dtb;
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< Sampler *sampler;
<
< int switchCount;
<
< // List of all ExecContexts.
< std::vector<Thread *> thread;
<
< #if 0
< /** Page table pointer. */
< PageTable *pTable;
---
> // SWContext *swCtx;
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> std::vector<CPUExecContext *> thread;
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< /** Pointer to the icache interface. */
---
> FunctionalMemory *mem;
>
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< /** Pointer to the dcache interface. */
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< /** Whether or not the CPU should defer its registration. */
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< /** Is there a context switch pending? */
< bool contextSwitch;
---
> Counter numInsts;
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< /** Threads Scheduled to Enter CPU */
< std::list<int> cpuWaitList;
<
< /** The cycle that the CPU was last running, used for statistics. */
< Tick lastRunningCycle;
<
< /** Number of Threads CPU can process */
< unsigned numThreads;
<
< /** Mapping for system thread id to cpu id */
< std::map<unsigned,unsigned> threadMap;
<
< /** Available thread ids in the cpu*/
< std::vector<unsigned> tids;
<
< /** Stat for total number of times the CPU is descheduled. */
< Stats::Scalar<> timesIdled;
< /** Stat for total number of cycles the CPU spends descheduled. */
< Stats::Scalar<> idleCycles;
< /** Stat for the number of committed instructions per thread. */
< Stats::Vector<> committedInsts;
< /** Stat for the total number of committed instructions. */
< Stats::Scalar<> totalCommittedInsts;
< /** Stat for the CPI per thread. */
< Stats::Formula cpi;
< /** Stat for the total CPI. */
< Stats::Formula totalCpi;
< /** Stat for the IPC per thread. */
< Stats::Formula ipc;
< /** Stat for the total IPC. */
< Stats::Formula totalIpc;
---
> Counter funcExeInst;
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< #endif // __CPU_O3_CPU_HH__
---
> #endif