109a110,111
> using VecPredRegContainer = TheISA::VecPredRegContainer;
>
459a462,465
> const VecPredRegContainer& readVecPredReg(PhysRegIdPtr reg_idx) const;
>
> VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr reg_idx);
>
469a476,477
> void setVecPredReg(PhysRegIdPtr reg_idx, const VecPredRegContainer& val);
>
503a512,516
> const VecPredRegContainer& readArchVecPredReg(int reg_idx,
> ThreadID tid) const;
>
> VecPredRegContainer& getWritableArchVecPredReg(int reg_idx, ThreadID tid);
>
514a528,530
> void setArchVecPredReg(int reg_idx, const VecPredRegContainer& val,
> ThreadID tid);
>
807a824,826
> //number of predicate register file accesses
> mutable Stats::Scalar vecPredRegfileReads;
> Stats::Scalar vecPredRegfileWrites;