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< * Copyright (c) 2011-2013 ARM Limited
---
> * Copyright (c) 2011-2013, 2016 ARM Limited
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> #include "arch/generic/types.hh"
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> using VecElem = TheISA::VecElem;
> using VecRegContainer = TheISA::VecRegContainer;
>
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> const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const;
>
> /**
> * Read physical vector register for modification.
> */
> VecRegContainer& getWritableVecReg(PhysRegIdPtr reg_idx);
>
> /**
> * Read physical vector register lane
> */
> template<typename VecElem, int LaneIdx>
> VecLaneT<VecElem, true>
> readVecLane(PhysRegIdPtr phys_reg) const
> {
> vecRegfileReads++;
> return regFile.readVecLane<VecElem, LaneIdx>(phys_reg);
> }
>
> /**
> * Read physical vector register lane
> */
> template<typename VecElem>
> VecLaneT<VecElem, true>
> readVecLane(PhysRegIdPtr phys_reg) const
> {
> vecRegfileReads++;
> return regFile.readVecLane<VecElem>(phys_reg);
> }
>
> /** Write a lane of the destination vector register. */
> template<typename LD>
> void
> setVecLane(PhysRegIdPtr phys_reg, const LD& val)
> {
> vecRegfileWrites++;
> return regFile.setVecLane(phys_reg, val);
> }
>
> const VecElem& readVecElem(PhysRegIdPtr reg_idx) const;
>
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> void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val);
>
> void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val);
>
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> const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const;
> /** Read architectural vector register for modification. */
> VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID tid);
>
> /** Read architectural vector register lane. */
> template<typename VecElem>
> VecLaneT<VecElem, true>
> readArchVecLane(int reg_idx, int lId, ThreadID tid) const
> {
> PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
> RegId(VecRegClass, reg_idx));
> return readVecLane<VecElem>(phys_reg);
> }
>
>
> /** Write a lane of the destination vector register. */
> template<typename LD>
> void
> setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val)
> {
> PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
> RegId(VecRegClass, reg_idx));
> setVecLane(phys_reg, val);
> }
>
> const VecElem& readArchVecElem(const RegIndex& reg_idx,
> const ElemIndex& ldx, ThreadID tid) const;
>
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> void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid);
>
> void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
> const VecElem& val, ThreadID tid);
>
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> /** The rename mode of the vector registers */
> Enums::VecRegRenameMode vecMode;
>
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> //number of vector register file accesses
> mutable Stats::Scalar vecRegfileReads;
> Stats::Scalar vecRegfileWrites;