1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 * Rick Strong
44 */
45
46#ifndef __CPU_O3_CPU_HH__
47#define __CPU_O3_CPU_HH__
48
49#include <iostream>
50#include <list>
51#include <queue>
52#include <set>
53#include <vector>
54
55#include "arch/types.hh"
56#include "base/statistics.hh"
57#include "config/the_isa.hh"
58#include "cpu/o3/comm.hh"
59#include "cpu/o3/cpu_policy.hh"
60#include "cpu/o3/scoreboard.hh"
61#include "cpu/o3/thread_state.hh"
62#include "cpu/activity.hh"
63#include "cpu/base.hh"
64#include "cpu/simple_thread.hh"
65#include "cpu/timebuf.hh"
66//#include "cpu/o3/thread_context.hh"
67#include "params/DerivO3CPU.hh"
68#include "sim/process.hh"
69
70template <class>
71class Checker;
72class ThreadContext;
73template <class>
74class O3ThreadContext;
75
76class Checkpoint;
77class MemObject;
78class Process;
79
80struct BaseCPUParams;
81
82class BaseO3CPU : public BaseCPU
83{
84 //Stuff that's pretty ISA independent will go here.
85 public:
86 BaseO3CPU(BaseCPUParams *params);
87
88 void regStats();
89};
90
91/**
92 * FullO3CPU class, has each of the stages (fetch through commit)
93 * within it, as well as all of the time buffers between stages. The
94 * tick() function for the CPU is defined here.
95 */
96template <class Impl>
97class FullO3CPU : public BaseO3CPU
98{
99 public:
100 // Typedefs from the Impl here.
101 typedef typename Impl::CPUPol CPUPolicy;
102 typedef typename Impl::DynInstPtr DynInstPtr;
103 typedef typename Impl::O3CPU O3CPU;
104
105 typedef O3ThreadState<Impl> ImplState;
106 typedef O3ThreadState<Impl> Thread;
107
108 typedef typename std::list<DynInstPtr>::iterator ListIt;
109
110 friend class O3ThreadContext<Impl>;
111
112 public:
113 enum Status {
114 Running,
115 Idle,
116 Halted,
117 Blocked,
118 SwitchedOut
119 };
120
121 TheISA::TLB * itb;
122 TheISA::TLB * dtb;
123
124 /** Overall CPU status. */
125 Status _status;
126
127 private:
128
129 /**
130 * IcachePort class for instruction fetch.
131 */
132 class IcachePort : public CpuPort
133 {
134 protected:
135 /** Pointer to fetch. */
136 DefaultFetch<Impl> *fetch;
137
138 public:
139 /** Default constructor. */
140 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
141 : CpuPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
142 { }
143
144 protected:
145
146 /** Timing version of receive. Handles setting fetch to the
147 * proper status to start fetching. */
148 virtual bool recvTimingResp(PacketPtr pkt);
149 virtual void recvTimingSnoopReq(PacketPtr pkt) { }
150
151 /** Handles doing a retry of a failed fetch. */
152 virtual void recvRetry();
153 };
154
155 /**
156 * DcachePort class for the load/store queue.
157 */
158 class DcachePort : public CpuPort
159 {
160 protected:
161
162 /** Pointer to LSQ. */
163 LSQ<Impl> *lsq;
164
165 public:
166 /** Default constructor. */
167 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
168 : CpuPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq)
169 { }
170
171 protected:
172
173 /** Timing version of receive. Handles writing back and
174 * completing the load or store that has returned from
175 * memory. */
176 virtual bool recvTimingResp(PacketPtr pkt);
177 virtual void recvTimingSnoopReq(PacketPtr pkt);
178
179 /** Handles doing a retry of the previous send. */
180 virtual void recvRetry();
181
182 /**
183 * As this CPU requires snooping to maintain the load store queue
184 * change the behaviour from the base CPU port.
185 *
186 * @return true since we have to snoop
187 */
188 virtual bool isSnooping() const { return true; }
189 };
190
191 class TickEvent : public Event
192 {
193 private:
194 /** Pointer to the CPU. */
195 FullO3CPU<Impl> *cpu;
196
197 public:
198 /** Constructs a tick event. */
199 TickEvent(FullO3CPU<Impl> *c);
200
201 /** Processes a tick event, calling tick() on the CPU. */
202 void process();
203 /** Returns the description of the tick event. */
204 const char *description() const;
205 };
206
207 /** The tick event used for scheduling CPU ticks. */
208 TickEvent tickEvent;
209
210 /** Schedule tick event, regardless of its current state. */
211 void scheduleTickEvent(Cycles delay)
212 {
213 if (tickEvent.squashed())
214 reschedule(tickEvent, clockEdge(delay));
215 else if (!tickEvent.scheduled())
216 schedule(tickEvent, clockEdge(delay));
217 }
218
219 /** Unschedule tick event, regardless of its current state. */
220 void unscheduleTickEvent()
221 {
222 if (tickEvent.scheduled())
223 tickEvent.squash();
224 }
225
226 class ActivateThreadEvent : public Event
227 {
228 private:
229 /** Number of Thread to Activate */
230 ThreadID tid;
231
232 /** Pointer to the CPU. */
233 FullO3CPU<Impl> *cpu;
234
235 public:
236 /** Constructs the event. */
237 ActivateThreadEvent();
238
239 /** Initialize Event */
240 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
241
242 /** Processes the event, calling activateThread() on the CPU. */
243 void process();
244
245 /** Returns the description of the event. */
246 const char *description() const;
247 };
248
249 /** Schedule thread to activate , regardless of its current state. */
250 void
251 scheduleActivateThreadEvent(ThreadID tid, Cycles delay)
252 {
253 // Schedule thread to activate, regardless of its current state.
254 if (activateThreadEvent[tid].squashed())
255 reschedule(activateThreadEvent[tid],
256 clockEdge(delay));
257 else if (!activateThreadEvent[tid].scheduled()) {
258 Tick when = clockEdge(delay);
259
260 // Check if the deallocateEvent is also scheduled, and make
261 // sure they do not happen at same time causing a sleep that
262 // is never woken from.
263 if (deallocateContextEvent[tid].scheduled() &&
264 deallocateContextEvent[tid].when() == when) {
265 when++;
266 }
267
268 schedule(activateThreadEvent[tid], when);
269 }
270 }
271
272 /** Unschedule actiavte thread event, regardless of its current state. */
273 void
274 unscheduleActivateThreadEvent(ThreadID tid)
275 {
276 if (activateThreadEvent[tid].scheduled())
277 activateThreadEvent[tid].squash();
278 }
279
280 /** The tick event used for scheduling CPU ticks. */
281 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
282
283 class DeallocateContextEvent : public Event
284 {
285 private:
286 /** Number of Thread to deactivate */
287 ThreadID tid;
288
289 /** Should the thread be removed from the CPU? */
290 bool remove;
291
292 /** Pointer to the CPU. */
293 FullO3CPU<Impl> *cpu;
294
295 public:
296 /** Constructs the event. */
297 DeallocateContextEvent();
298
299 /** Initialize Event */
300 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
301
302 /** Processes the event, calling activateThread() on the CPU. */
303 void process();
304
305 /** Sets whether the thread should also be removed from the CPU. */
306 void setRemove(bool _remove) { remove = _remove; }
307
308 /** Returns the description of the event. */
309 const char *description() const;
310 };
311
312 /** Schedule cpu to deallocate thread context.*/
313 void
314 scheduleDeallocateContextEvent(ThreadID tid, bool remove, Cycles delay)
315 {
316 // Schedule thread to activate, regardless of its current state.
317 if (deallocateContextEvent[tid].squashed())
318 reschedule(deallocateContextEvent[tid],
319 clockEdge(delay));
320 else if (!deallocateContextEvent[tid].scheduled())
321 schedule(deallocateContextEvent[tid],
322 clockEdge(delay));
323 }
324
325 /** Unschedule thread deallocation in CPU */
326 void
327 unscheduleDeallocateContextEvent(ThreadID tid)
328 {
329 if (deallocateContextEvent[tid].scheduled())
330 deallocateContextEvent[tid].squash();
331 }
332
333 /** The tick event used for scheduling CPU ticks. */
334 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
335
336 /**
337 * Check if the pipeline has drained and signal the DrainManager.
338 *
339 * This method checks if a drain has been requested and if the CPU
340 * has drained successfully (i.e., there are no instructions in
341 * the pipeline). If the CPU has drained, it deschedules the tick
342 * event and signals the drain manager.
343 *
344 * @return False if a drain hasn't been requested or the CPU
345 * hasn't drained, true otherwise.
346 */
347 bool tryDrain();
348
349 /**
350 * Perform sanity checks after a drain.
351 *
352 * This method is called from drain() when it has determined that
353 * the CPU is fully drained when gem5 is compiled with the NDEBUG
354 * macro undefined. The intention of this method is to do more
355 * extensive tests than the isDrained() method to weed out any
356 * draining bugs.
357 */
358 void drainSanityCheck() const;
359
360 /** Check if a system is in a drained state. */
361 bool isDrained() const;
362
363 public:
364 /** Constructs a CPU with the given parameters. */
365 FullO3CPU(DerivO3CPUParams *params);
366 /** Destructor. */
367 ~FullO3CPU();
368
369 /** Registers statistics. */
370 void regStats();
371
372 void demapPage(Addr vaddr, uint64_t asn)
373 {
374 this->itb->demapPage(vaddr, asn);
375 this->dtb->demapPage(vaddr, asn);
376 }
377
378 void demapInstPage(Addr vaddr, uint64_t asn)
379 {
380 this->itb->demapPage(vaddr, asn);
381 }
382
383 void demapDataPage(Addr vaddr, uint64_t asn)
384 {
385 this->dtb->demapPage(vaddr, asn);
386 }
387
388 /** Ticks CPU, calling tick() on each stage, and checking the overall
389 * activity to see if the CPU should deschedule itself.
390 */
391 void tick();
392
393 /** Initialize the CPU */
394 void init();
395
396 void startup();
397
398 /** Returns the Number of Active Threads in the CPU */
399 int numActiveThreads()
400 { return activeThreads.size(); }
401
402 /** Add Thread to Active Threads List */
403 void activateThread(ThreadID tid);
404
405 /** Remove Thread from Active Threads List */
406 void deactivateThread(ThreadID tid);
407
408 /** Setup CPU to insert a thread's context */
409 void insertThread(ThreadID tid);
410
411 /** Remove all of a thread's context from CPU */
412 void removeThread(ThreadID tid);
413
414 /** Count the Total Instructions Committed in the CPU. */
415 virtual Counter totalInsts() const;
416
417 /** Count the Total Ops (including micro ops) committed in the CPU. */
418 virtual Counter totalOps() const;
419
420 /** Add Thread to Active Threads List. */
421 void activateContext(ThreadID tid, Cycles delay);
422
423 /** Remove Thread from Active Threads List */
424 void suspendContext(ThreadID tid);
425
426 /** Remove Thread from Active Threads List &&
427 * Possibly Remove Thread Context from CPU.
428 */
429 bool scheduleDeallocateContext(ThreadID tid, bool remove,
430 Cycles delay = Cycles(1));
431
432 /** Remove Thread from Active Threads List &&
433 * Remove Thread Context from CPU.
434 */
435 void haltContext(ThreadID tid);
436
437 /** Activate a Thread When CPU Resources are Available. */
438 void activateWhenReady(ThreadID tid);
439
440 /** Add or Remove a Thread Context in the CPU. */
441 void doContextSwitch();
442
443 /** Update The Order In Which We Process Threads. */
444 void updateThreadPriority();
445
446 /** Is the CPU draining? */
447 bool isDraining() const { return getDrainState() == Drainable::Draining; }
448
| 1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 * Rick Strong
44 */
45
46#ifndef __CPU_O3_CPU_HH__
47#define __CPU_O3_CPU_HH__
48
49#include <iostream>
50#include <list>
51#include <queue>
52#include <set>
53#include <vector>
54
55#include "arch/types.hh"
56#include "base/statistics.hh"
57#include "config/the_isa.hh"
58#include "cpu/o3/comm.hh"
59#include "cpu/o3/cpu_policy.hh"
60#include "cpu/o3/scoreboard.hh"
61#include "cpu/o3/thread_state.hh"
62#include "cpu/activity.hh"
63#include "cpu/base.hh"
64#include "cpu/simple_thread.hh"
65#include "cpu/timebuf.hh"
66//#include "cpu/o3/thread_context.hh"
67#include "params/DerivO3CPU.hh"
68#include "sim/process.hh"
69
70template <class>
71class Checker;
72class ThreadContext;
73template <class>
74class O3ThreadContext;
75
76class Checkpoint;
77class MemObject;
78class Process;
79
80struct BaseCPUParams;
81
82class BaseO3CPU : public BaseCPU
83{
84 //Stuff that's pretty ISA independent will go here.
85 public:
86 BaseO3CPU(BaseCPUParams *params);
87
88 void regStats();
89};
90
91/**
92 * FullO3CPU class, has each of the stages (fetch through commit)
93 * within it, as well as all of the time buffers between stages. The
94 * tick() function for the CPU is defined here.
95 */
96template <class Impl>
97class FullO3CPU : public BaseO3CPU
98{
99 public:
100 // Typedefs from the Impl here.
101 typedef typename Impl::CPUPol CPUPolicy;
102 typedef typename Impl::DynInstPtr DynInstPtr;
103 typedef typename Impl::O3CPU O3CPU;
104
105 typedef O3ThreadState<Impl> ImplState;
106 typedef O3ThreadState<Impl> Thread;
107
108 typedef typename std::list<DynInstPtr>::iterator ListIt;
109
110 friend class O3ThreadContext<Impl>;
111
112 public:
113 enum Status {
114 Running,
115 Idle,
116 Halted,
117 Blocked,
118 SwitchedOut
119 };
120
121 TheISA::TLB * itb;
122 TheISA::TLB * dtb;
123
124 /** Overall CPU status. */
125 Status _status;
126
127 private:
128
129 /**
130 * IcachePort class for instruction fetch.
131 */
132 class IcachePort : public CpuPort
133 {
134 protected:
135 /** Pointer to fetch. */
136 DefaultFetch<Impl> *fetch;
137
138 public:
139 /** Default constructor. */
140 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
141 : CpuPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
142 { }
143
144 protected:
145
146 /** Timing version of receive. Handles setting fetch to the
147 * proper status to start fetching. */
148 virtual bool recvTimingResp(PacketPtr pkt);
149 virtual void recvTimingSnoopReq(PacketPtr pkt) { }
150
151 /** Handles doing a retry of a failed fetch. */
152 virtual void recvRetry();
153 };
154
155 /**
156 * DcachePort class for the load/store queue.
157 */
158 class DcachePort : public CpuPort
159 {
160 protected:
161
162 /** Pointer to LSQ. */
163 LSQ<Impl> *lsq;
164
165 public:
166 /** Default constructor. */
167 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
168 : CpuPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq)
169 { }
170
171 protected:
172
173 /** Timing version of receive. Handles writing back and
174 * completing the load or store that has returned from
175 * memory. */
176 virtual bool recvTimingResp(PacketPtr pkt);
177 virtual void recvTimingSnoopReq(PacketPtr pkt);
178
179 /** Handles doing a retry of the previous send. */
180 virtual void recvRetry();
181
182 /**
183 * As this CPU requires snooping to maintain the load store queue
184 * change the behaviour from the base CPU port.
185 *
186 * @return true since we have to snoop
187 */
188 virtual bool isSnooping() const { return true; }
189 };
190
191 class TickEvent : public Event
192 {
193 private:
194 /** Pointer to the CPU. */
195 FullO3CPU<Impl> *cpu;
196
197 public:
198 /** Constructs a tick event. */
199 TickEvent(FullO3CPU<Impl> *c);
200
201 /** Processes a tick event, calling tick() on the CPU. */
202 void process();
203 /** Returns the description of the tick event. */
204 const char *description() const;
205 };
206
207 /** The tick event used for scheduling CPU ticks. */
208 TickEvent tickEvent;
209
210 /** Schedule tick event, regardless of its current state. */
211 void scheduleTickEvent(Cycles delay)
212 {
213 if (tickEvent.squashed())
214 reschedule(tickEvent, clockEdge(delay));
215 else if (!tickEvent.scheduled())
216 schedule(tickEvent, clockEdge(delay));
217 }
218
219 /** Unschedule tick event, regardless of its current state. */
220 void unscheduleTickEvent()
221 {
222 if (tickEvent.scheduled())
223 tickEvent.squash();
224 }
225
226 class ActivateThreadEvent : public Event
227 {
228 private:
229 /** Number of Thread to Activate */
230 ThreadID tid;
231
232 /** Pointer to the CPU. */
233 FullO3CPU<Impl> *cpu;
234
235 public:
236 /** Constructs the event. */
237 ActivateThreadEvent();
238
239 /** Initialize Event */
240 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
241
242 /** Processes the event, calling activateThread() on the CPU. */
243 void process();
244
245 /** Returns the description of the event. */
246 const char *description() const;
247 };
248
249 /** Schedule thread to activate , regardless of its current state. */
250 void
251 scheduleActivateThreadEvent(ThreadID tid, Cycles delay)
252 {
253 // Schedule thread to activate, regardless of its current state.
254 if (activateThreadEvent[tid].squashed())
255 reschedule(activateThreadEvent[tid],
256 clockEdge(delay));
257 else if (!activateThreadEvent[tid].scheduled()) {
258 Tick when = clockEdge(delay);
259
260 // Check if the deallocateEvent is also scheduled, and make
261 // sure they do not happen at same time causing a sleep that
262 // is never woken from.
263 if (deallocateContextEvent[tid].scheduled() &&
264 deallocateContextEvent[tid].when() == when) {
265 when++;
266 }
267
268 schedule(activateThreadEvent[tid], when);
269 }
270 }
271
272 /** Unschedule actiavte thread event, regardless of its current state. */
273 void
274 unscheduleActivateThreadEvent(ThreadID tid)
275 {
276 if (activateThreadEvent[tid].scheduled())
277 activateThreadEvent[tid].squash();
278 }
279
280 /** The tick event used for scheduling CPU ticks. */
281 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
282
283 class DeallocateContextEvent : public Event
284 {
285 private:
286 /** Number of Thread to deactivate */
287 ThreadID tid;
288
289 /** Should the thread be removed from the CPU? */
290 bool remove;
291
292 /** Pointer to the CPU. */
293 FullO3CPU<Impl> *cpu;
294
295 public:
296 /** Constructs the event. */
297 DeallocateContextEvent();
298
299 /** Initialize Event */
300 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
301
302 /** Processes the event, calling activateThread() on the CPU. */
303 void process();
304
305 /** Sets whether the thread should also be removed from the CPU. */
306 void setRemove(bool _remove) { remove = _remove; }
307
308 /** Returns the description of the event. */
309 const char *description() const;
310 };
311
312 /** Schedule cpu to deallocate thread context.*/
313 void
314 scheduleDeallocateContextEvent(ThreadID tid, bool remove, Cycles delay)
315 {
316 // Schedule thread to activate, regardless of its current state.
317 if (deallocateContextEvent[tid].squashed())
318 reschedule(deallocateContextEvent[tid],
319 clockEdge(delay));
320 else if (!deallocateContextEvent[tid].scheduled())
321 schedule(deallocateContextEvent[tid],
322 clockEdge(delay));
323 }
324
325 /** Unschedule thread deallocation in CPU */
326 void
327 unscheduleDeallocateContextEvent(ThreadID tid)
328 {
329 if (deallocateContextEvent[tid].scheduled())
330 deallocateContextEvent[tid].squash();
331 }
332
333 /** The tick event used for scheduling CPU ticks. */
334 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
335
336 /**
337 * Check if the pipeline has drained and signal the DrainManager.
338 *
339 * This method checks if a drain has been requested and if the CPU
340 * has drained successfully (i.e., there are no instructions in
341 * the pipeline). If the CPU has drained, it deschedules the tick
342 * event and signals the drain manager.
343 *
344 * @return False if a drain hasn't been requested or the CPU
345 * hasn't drained, true otherwise.
346 */
347 bool tryDrain();
348
349 /**
350 * Perform sanity checks after a drain.
351 *
352 * This method is called from drain() when it has determined that
353 * the CPU is fully drained when gem5 is compiled with the NDEBUG
354 * macro undefined. The intention of this method is to do more
355 * extensive tests than the isDrained() method to weed out any
356 * draining bugs.
357 */
358 void drainSanityCheck() const;
359
360 /** Check if a system is in a drained state. */
361 bool isDrained() const;
362
363 public:
364 /** Constructs a CPU with the given parameters. */
365 FullO3CPU(DerivO3CPUParams *params);
366 /** Destructor. */
367 ~FullO3CPU();
368
369 /** Registers statistics. */
370 void regStats();
371
372 void demapPage(Addr vaddr, uint64_t asn)
373 {
374 this->itb->demapPage(vaddr, asn);
375 this->dtb->demapPage(vaddr, asn);
376 }
377
378 void demapInstPage(Addr vaddr, uint64_t asn)
379 {
380 this->itb->demapPage(vaddr, asn);
381 }
382
383 void demapDataPage(Addr vaddr, uint64_t asn)
384 {
385 this->dtb->demapPage(vaddr, asn);
386 }
387
388 /** Ticks CPU, calling tick() on each stage, and checking the overall
389 * activity to see if the CPU should deschedule itself.
390 */
391 void tick();
392
393 /** Initialize the CPU */
394 void init();
395
396 void startup();
397
398 /** Returns the Number of Active Threads in the CPU */
399 int numActiveThreads()
400 { return activeThreads.size(); }
401
402 /** Add Thread to Active Threads List */
403 void activateThread(ThreadID tid);
404
405 /** Remove Thread from Active Threads List */
406 void deactivateThread(ThreadID tid);
407
408 /** Setup CPU to insert a thread's context */
409 void insertThread(ThreadID tid);
410
411 /** Remove all of a thread's context from CPU */
412 void removeThread(ThreadID tid);
413
414 /** Count the Total Instructions Committed in the CPU. */
415 virtual Counter totalInsts() const;
416
417 /** Count the Total Ops (including micro ops) committed in the CPU. */
418 virtual Counter totalOps() const;
419
420 /** Add Thread to Active Threads List. */
421 void activateContext(ThreadID tid, Cycles delay);
422
423 /** Remove Thread from Active Threads List */
424 void suspendContext(ThreadID tid);
425
426 /** Remove Thread from Active Threads List &&
427 * Possibly Remove Thread Context from CPU.
428 */
429 bool scheduleDeallocateContext(ThreadID tid, bool remove,
430 Cycles delay = Cycles(1));
431
432 /** Remove Thread from Active Threads List &&
433 * Remove Thread Context from CPU.
434 */
435 void haltContext(ThreadID tid);
436
437 /** Activate a Thread When CPU Resources are Available. */
438 void activateWhenReady(ThreadID tid);
439
440 /** Add or Remove a Thread Context in the CPU. */
441 void doContextSwitch();
442
443 /** Update The Order In Which We Process Threads. */
444 void updateThreadPriority();
445
446 /** Is the CPU draining? */
447 bool isDraining() const { return getDrainState() == Drainable::Draining; }
448
|
454
455 public:
456 /** Executes a syscall.
457 * @todo: Determine if this needs to be virtual.
458 */
459 void syscall(int64_t callnum, ThreadID tid);
460
461 /** Starts draining the CPU's pipeline of all instructions in
462 * order to stop all memory accesses. */
463 unsigned int drain(DrainManager *drain_manager);
464
465 /** Resumes execution after a drain. */
466 void drainResume();
467
468 /**
469 * Commit has reached a safe point to drain a thread.
470 *
471 * Commit calls this method to inform the pipeline that it has
472 * reached a point where it is not executed microcode and is about
473 * to squash uncommitted instructions to fully drain the pipeline.
474 */
475 void commitDrained(ThreadID tid);
476
477 /** Switches out this CPU. */
478 virtual void switchOut();
479
480 /** Takes over from another CPU. */
481 virtual void takeOverFrom(BaseCPU *oldCPU);
482
483 /** Get the current instruction sequence number, and increment it. */
484 InstSeqNum getAndIncrementInstSeq()
485 { return globalSeqNum++; }
486
487 /** Traps to handle given fault. */
488 void trap(Fault fault, ThreadID tid, StaticInstPtr inst);
489
490 /** HW return from error interrupt. */
491 Fault hwrei(ThreadID tid);
492
493 bool simPalCheck(int palFunc, ThreadID tid);
494
495 /** Returns the Fault for any valid interrupt. */
496 Fault getInterrupts();
497
498 /** Processes any an interrupt fault. */
499 void processInterrupts(Fault interrupt);
500
501 /** Halts the CPU. */
502 void halt() { panic("Halt not implemented!\n"); }
503
504 /** Check if this address is a valid instruction address. */
505 bool validInstAddr(Addr addr) { return true; }
506
507 /** Check if this address is a valid data address. */
508 bool validDataAddr(Addr addr) { return true; }
509
510 /** Register accessors. Index refers to the physical register index. */
511
512 /** Reads a miscellaneous register. */
513 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
514
515 /** Reads a misc. register, including any side effects the read
516 * might have as defined by the architecture.
517 */
518 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
519
520 /** Sets a miscellaneous register. */
521 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
522 ThreadID tid);
523
524 /** Sets a misc. register, including any side effects the write
525 * might have as defined by the architecture.
526 */
527 void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
528 ThreadID tid);
529
530 uint64_t readIntReg(int reg_idx);
531
532 TheISA::FloatReg readFloatReg(int reg_idx);
533
534 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
535
536 void setIntReg(int reg_idx, uint64_t val);
537
538 void setFloatReg(int reg_idx, TheISA::FloatReg val);
539
540 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
541
542 uint64_t readArchIntReg(int reg_idx, ThreadID tid);
543
544 float readArchFloatReg(int reg_idx, ThreadID tid);
545
546 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
547
548 /** Architectural register accessors. Looks up in the commit
549 * rename table to obtain the true physical index of the
550 * architected register first, then accesses that physical
551 * register.
552 */
553 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
554
555 void setArchFloatReg(int reg_idx, float val, ThreadID tid);
556
557 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
558
559 /** Sets the commit PC state of a specific thread. */
560 void pcState(const TheISA::PCState &newPCState, ThreadID tid);
561
562 /** Reads the commit PC state of a specific thread. */
563 TheISA::PCState pcState(ThreadID tid);
564
565 /** Reads the commit PC of a specific thread. */
566 Addr instAddr(ThreadID tid);
567
568 /** Reads the commit micro PC of a specific thread. */
569 MicroPC microPC(ThreadID tid);
570
571 /** Reads the next PC of a specific thread. */
572 Addr nextInstAddr(ThreadID tid);
573
574 /** Initiates a squash of all in-flight instructions for a given
575 * thread. The source of the squash is an external update of
576 * state through the TC.
577 */
578 void squashFromTC(ThreadID tid);
579
580 /** Function to add instruction onto the head of the list of the
581 * instructions. Used when new instructions are fetched.
582 */
583 ListIt addInst(DynInstPtr &inst);
584
585 /** Function to tell the CPU that an instruction has completed. */
586 void instDone(ThreadID tid, DynInstPtr &inst);
587
588 /** Remove an instruction from the front end of the list. There's
589 * no restriction on location of the instruction.
590 */
591 void removeFrontInst(DynInstPtr &inst);
592
593 /** Remove all instructions that are not currently in the ROB.
594 * There's also an option to not squash delay slot instructions.*/
595 void removeInstsNotInROB(ThreadID tid);
596
597 /** Remove all instructions younger than the given sequence number. */
598 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
599
600 /** Removes the instruction pointed to by the iterator. */
601 inline void squashInstIt(const ListIt &instIt, ThreadID tid);
602
603 /** Cleans up all instructions on the remove list. */
604 void cleanUpRemovedInsts();
605
606 /** Debug function to print all instructions on the list. */
607 void dumpInsts();
608
609 public:
610#ifndef NDEBUG
611 /** Count of total number of dynamic instructions in flight. */
612 int instcount;
613#endif
614
615 /** List of all the instructions in flight. */
616 std::list<DynInstPtr> instList;
617
618 /** List of all the instructions that will be removed at the end of this
619 * cycle.
620 */
621 std::queue<ListIt> removeList;
622
623#ifdef DEBUG
624 /** Debug structure to keep track of the sequence numbers still in
625 * flight.
626 */
627 std::set<InstSeqNum> snList;
628#endif
629
630 /** Records if instructions need to be removed this cycle due to
631 * being retired or squashed.
632 */
633 bool removeInstsThisCycle;
634
635 protected:
636 /** The fetch stage. */
637 typename CPUPolicy::Fetch fetch;
638
639 /** The decode stage. */
640 typename CPUPolicy::Decode decode;
641
642 /** The dispatch stage. */
643 typename CPUPolicy::Rename rename;
644
645 /** The issue/execute/writeback stages. */
646 typename CPUPolicy::IEW iew;
647
648 /** The commit stage. */
649 typename CPUPolicy::Commit commit;
650
651 /** The register file. */
652 typename CPUPolicy::RegFile regFile;
653
654 /** The free list. */
655 typename CPUPolicy::FreeList freeList;
656
657 /** The rename map. */
658 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
659
660 /** The commit rename map. */
661 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
662
663 /** The re-order buffer. */
664 typename CPUPolicy::ROB rob;
665
666 /** Active Threads List */
667 std::list<ThreadID> activeThreads;
668
669 /** Integer Register Scoreboard */
670 Scoreboard scoreboard;
671
672 std::vector<TheISA::ISA *> isa;
673
674 /** Instruction port. Note that it has to appear after the fetch stage. */
675 IcachePort icachePort;
676
677 /** Data port. Note that it has to appear after the iew stages */
678 DcachePort dcachePort;
679
680 public:
681 /** Enum to give each stage a specific index, so when calling
682 * activateStage() or deactivateStage(), they can specify which stage
683 * is being activated/deactivated.
684 */
685 enum StageIdx {
686 FetchIdx,
687 DecodeIdx,
688 RenameIdx,
689 IEWIdx,
690 CommitIdx,
691 NumStages };
692
693 /** Typedefs from the Impl to get the structs that each of the
694 * time buffers should use.
695 */
696 typedef typename CPUPolicy::TimeStruct TimeStruct;
697
698 typedef typename CPUPolicy::FetchStruct FetchStruct;
699
700 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
701
702 typedef typename CPUPolicy::RenameStruct RenameStruct;
703
704 typedef typename CPUPolicy::IEWStruct IEWStruct;
705
706 /** The main time buffer to do backwards communication. */
707 TimeBuffer<TimeStruct> timeBuffer;
708
709 /** The fetch stage's instruction queue. */
710 TimeBuffer<FetchStruct> fetchQueue;
711
712 /** The decode stage's instruction queue. */
713 TimeBuffer<DecodeStruct> decodeQueue;
714
715 /** The rename stage's instruction queue. */
716 TimeBuffer<RenameStruct> renameQueue;
717
718 /** The IEW stage's instruction queue. */
719 TimeBuffer<IEWStruct> iewQueue;
720
721 private:
722 /** The activity recorder; used to tell if the CPU has any
723 * activity remaining or if it can go to idle and deschedule
724 * itself.
725 */
726 ActivityRecorder activityRec;
727
728 public:
729 /** Records that there was time buffer activity this cycle. */
730 void activityThisCycle() { activityRec.activity(); }
731
732 /** Changes a stage's status to active within the activity recorder. */
733 void activateStage(const StageIdx idx)
734 { activityRec.activateStage(idx); }
735
736 /** Changes a stage's status to inactive within the activity recorder. */
737 void deactivateStage(const StageIdx idx)
738 { activityRec.deactivateStage(idx); }
739
740 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
741 void wakeCPU();
742
743 virtual void wakeup();
744
745 /** Gets a free thread id. Use if thread ids change across system. */
746 ThreadID getFreeTid();
747
748 public:
749 /** Returns a pointer to a thread context. */
750 ThreadContext *
751 tcBase(ThreadID tid)
752 {
753 return thread[tid]->getTC();
754 }
755
756 /** The global sequence number counter. */
757 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
758
759 /** Pointer to the checker, which can dynamically verify
760 * instruction results at run time. This can be set to NULL if it
761 * is not being used.
762 */
763 Checker<Impl> *checker;
764
765 /** Pointer to the system. */
766 System *system;
767
768 /** DrainManager to notify when draining has completed. */
769 DrainManager *drainManager;
770
771 /** Pointers to all of the threads in the CPU. */
772 std::vector<Thread *> thread;
773
774 /** Is there a context switch pending? */
775 bool contextSwitch;
776
777 /** Threads Scheduled to Enter CPU */
778 std::list<int> cpuWaitList;
779
780 /** The cycle that the CPU was last running, used for statistics. */
781 Cycles lastRunningCycle;
782
783 /** The cycle that the CPU was last activated by a new thread*/
784 Tick lastActivatedCycle;
785
786 /** Mapping for system thread id to cpu id */
787 std::map<ThreadID, unsigned> threadMap;
788
789 /** Available thread ids in the cpu*/
790 std::vector<ThreadID> tids;
791
792 /** CPU read function, forwards read to LSQ. */
793 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
794 uint8_t *data, int load_idx)
795 {
796 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh,
797 data, load_idx);
798 }
799
800 /** CPU write function, forwards write to LSQ. */
801 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
802 uint8_t *data, int store_idx)
803 {
804 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
805 data, store_idx);
806 }
807
808 /** Used by the fetch unit to get a hold of the instruction port. */
809 virtual CpuPort &getInstPort() { return icachePort; }
810
811 /** Get the dcache port (used to find block size for translations). */
812 virtual CpuPort &getDataPort() { return dcachePort; }
813
814 /** Stat for total number of times the CPU is descheduled. */
815 Stats::Scalar timesIdled;
816 /** Stat for total number of cycles the CPU spends descheduled. */
817 Stats::Scalar idleCycles;
818 /** Stat for total number of cycles the CPU spends descheduled due to a
819 * quiesce operation or waiting for an interrupt. */
820 Stats::Scalar quiesceCycles;
821 /** Stat for the number of committed instructions per thread. */
822 Stats::Vector committedInsts;
823 /** Stat for the number of committed ops (including micro ops) per thread. */
824 Stats::Vector committedOps;
825 /** Stat for the total number of committed instructions. */
826 Stats::Scalar totalCommittedInsts;
827 /** Stat for the CPI per thread. */
828 Stats::Formula cpi;
829 /** Stat for the total CPI. */
830 Stats::Formula totalCpi;
831 /** Stat for the IPC per thread. */
832 Stats::Formula ipc;
833 /** Stat for the total IPC. */
834 Stats::Formula totalIpc;
835
836 //number of integer register file accesses
837 Stats::Scalar intRegfileReads;
838 Stats::Scalar intRegfileWrites;
839 //number of float register file accesses
840 Stats::Scalar fpRegfileReads;
841 Stats::Scalar fpRegfileWrites;
842 //number of misc
843 Stats::Scalar miscRegfileReads;
844 Stats::Scalar miscRegfileWrites;
845};
846
847#endif // __CPU_O3_CPU_HH__
| 453
454 public:
455 /** Executes a syscall.
456 * @todo: Determine if this needs to be virtual.
457 */
458 void syscall(int64_t callnum, ThreadID tid);
459
460 /** Starts draining the CPU's pipeline of all instructions in
461 * order to stop all memory accesses. */
462 unsigned int drain(DrainManager *drain_manager);
463
464 /** Resumes execution after a drain. */
465 void drainResume();
466
467 /**
468 * Commit has reached a safe point to drain a thread.
469 *
470 * Commit calls this method to inform the pipeline that it has
471 * reached a point where it is not executed microcode and is about
472 * to squash uncommitted instructions to fully drain the pipeline.
473 */
474 void commitDrained(ThreadID tid);
475
476 /** Switches out this CPU. */
477 virtual void switchOut();
478
479 /** Takes over from another CPU. */
480 virtual void takeOverFrom(BaseCPU *oldCPU);
481
482 /** Get the current instruction sequence number, and increment it. */
483 InstSeqNum getAndIncrementInstSeq()
484 { return globalSeqNum++; }
485
486 /** Traps to handle given fault. */
487 void trap(Fault fault, ThreadID tid, StaticInstPtr inst);
488
489 /** HW return from error interrupt. */
490 Fault hwrei(ThreadID tid);
491
492 bool simPalCheck(int palFunc, ThreadID tid);
493
494 /** Returns the Fault for any valid interrupt. */
495 Fault getInterrupts();
496
497 /** Processes any an interrupt fault. */
498 void processInterrupts(Fault interrupt);
499
500 /** Halts the CPU. */
501 void halt() { panic("Halt not implemented!\n"); }
502
503 /** Check if this address is a valid instruction address. */
504 bool validInstAddr(Addr addr) { return true; }
505
506 /** Check if this address is a valid data address. */
507 bool validDataAddr(Addr addr) { return true; }
508
509 /** Register accessors. Index refers to the physical register index. */
510
511 /** Reads a miscellaneous register. */
512 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
513
514 /** Reads a misc. register, including any side effects the read
515 * might have as defined by the architecture.
516 */
517 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
518
519 /** Sets a miscellaneous register. */
520 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
521 ThreadID tid);
522
523 /** Sets a misc. register, including any side effects the write
524 * might have as defined by the architecture.
525 */
526 void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
527 ThreadID tid);
528
529 uint64_t readIntReg(int reg_idx);
530
531 TheISA::FloatReg readFloatReg(int reg_idx);
532
533 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
534
535 void setIntReg(int reg_idx, uint64_t val);
536
537 void setFloatReg(int reg_idx, TheISA::FloatReg val);
538
539 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
540
541 uint64_t readArchIntReg(int reg_idx, ThreadID tid);
542
543 float readArchFloatReg(int reg_idx, ThreadID tid);
544
545 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
546
547 /** Architectural register accessors. Looks up in the commit
548 * rename table to obtain the true physical index of the
549 * architected register first, then accesses that physical
550 * register.
551 */
552 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
553
554 void setArchFloatReg(int reg_idx, float val, ThreadID tid);
555
556 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
557
558 /** Sets the commit PC state of a specific thread. */
559 void pcState(const TheISA::PCState &newPCState, ThreadID tid);
560
561 /** Reads the commit PC state of a specific thread. */
562 TheISA::PCState pcState(ThreadID tid);
563
564 /** Reads the commit PC of a specific thread. */
565 Addr instAddr(ThreadID tid);
566
567 /** Reads the commit micro PC of a specific thread. */
568 MicroPC microPC(ThreadID tid);
569
570 /** Reads the next PC of a specific thread. */
571 Addr nextInstAddr(ThreadID tid);
572
573 /** Initiates a squash of all in-flight instructions for a given
574 * thread. The source of the squash is an external update of
575 * state through the TC.
576 */
577 void squashFromTC(ThreadID tid);
578
579 /** Function to add instruction onto the head of the list of the
580 * instructions. Used when new instructions are fetched.
581 */
582 ListIt addInst(DynInstPtr &inst);
583
584 /** Function to tell the CPU that an instruction has completed. */
585 void instDone(ThreadID tid, DynInstPtr &inst);
586
587 /** Remove an instruction from the front end of the list. There's
588 * no restriction on location of the instruction.
589 */
590 void removeFrontInst(DynInstPtr &inst);
591
592 /** Remove all instructions that are not currently in the ROB.
593 * There's also an option to not squash delay slot instructions.*/
594 void removeInstsNotInROB(ThreadID tid);
595
596 /** Remove all instructions younger than the given sequence number. */
597 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
598
599 /** Removes the instruction pointed to by the iterator. */
600 inline void squashInstIt(const ListIt &instIt, ThreadID tid);
601
602 /** Cleans up all instructions on the remove list. */
603 void cleanUpRemovedInsts();
604
605 /** Debug function to print all instructions on the list. */
606 void dumpInsts();
607
608 public:
609#ifndef NDEBUG
610 /** Count of total number of dynamic instructions in flight. */
611 int instcount;
612#endif
613
614 /** List of all the instructions in flight. */
615 std::list<DynInstPtr> instList;
616
617 /** List of all the instructions that will be removed at the end of this
618 * cycle.
619 */
620 std::queue<ListIt> removeList;
621
622#ifdef DEBUG
623 /** Debug structure to keep track of the sequence numbers still in
624 * flight.
625 */
626 std::set<InstSeqNum> snList;
627#endif
628
629 /** Records if instructions need to be removed this cycle due to
630 * being retired or squashed.
631 */
632 bool removeInstsThisCycle;
633
634 protected:
635 /** The fetch stage. */
636 typename CPUPolicy::Fetch fetch;
637
638 /** The decode stage. */
639 typename CPUPolicy::Decode decode;
640
641 /** The dispatch stage. */
642 typename CPUPolicy::Rename rename;
643
644 /** The issue/execute/writeback stages. */
645 typename CPUPolicy::IEW iew;
646
647 /** The commit stage. */
648 typename CPUPolicy::Commit commit;
649
650 /** The register file. */
651 typename CPUPolicy::RegFile regFile;
652
653 /** The free list. */
654 typename CPUPolicy::FreeList freeList;
655
656 /** The rename map. */
657 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
658
659 /** The commit rename map. */
660 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
661
662 /** The re-order buffer. */
663 typename CPUPolicy::ROB rob;
664
665 /** Active Threads List */
666 std::list<ThreadID> activeThreads;
667
668 /** Integer Register Scoreboard */
669 Scoreboard scoreboard;
670
671 std::vector<TheISA::ISA *> isa;
672
673 /** Instruction port. Note that it has to appear after the fetch stage. */
674 IcachePort icachePort;
675
676 /** Data port. Note that it has to appear after the iew stages */
677 DcachePort dcachePort;
678
679 public:
680 /** Enum to give each stage a specific index, so when calling
681 * activateStage() or deactivateStage(), they can specify which stage
682 * is being activated/deactivated.
683 */
684 enum StageIdx {
685 FetchIdx,
686 DecodeIdx,
687 RenameIdx,
688 IEWIdx,
689 CommitIdx,
690 NumStages };
691
692 /** Typedefs from the Impl to get the structs that each of the
693 * time buffers should use.
694 */
695 typedef typename CPUPolicy::TimeStruct TimeStruct;
696
697 typedef typename CPUPolicy::FetchStruct FetchStruct;
698
699 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
700
701 typedef typename CPUPolicy::RenameStruct RenameStruct;
702
703 typedef typename CPUPolicy::IEWStruct IEWStruct;
704
705 /** The main time buffer to do backwards communication. */
706 TimeBuffer<TimeStruct> timeBuffer;
707
708 /** The fetch stage's instruction queue. */
709 TimeBuffer<FetchStruct> fetchQueue;
710
711 /** The decode stage's instruction queue. */
712 TimeBuffer<DecodeStruct> decodeQueue;
713
714 /** The rename stage's instruction queue. */
715 TimeBuffer<RenameStruct> renameQueue;
716
717 /** The IEW stage's instruction queue. */
718 TimeBuffer<IEWStruct> iewQueue;
719
720 private:
721 /** The activity recorder; used to tell if the CPU has any
722 * activity remaining or if it can go to idle and deschedule
723 * itself.
724 */
725 ActivityRecorder activityRec;
726
727 public:
728 /** Records that there was time buffer activity this cycle. */
729 void activityThisCycle() { activityRec.activity(); }
730
731 /** Changes a stage's status to active within the activity recorder. */
732 void activateStage(const StageIdx idx)
733 { activityRec.activateStage(idx); }
734
735 /** Changes a stage's status to inactive within the activity recorder. */
736 void deactivateStage(const StageIdx idx)
737 { activityRec.deactivateStage(idx); }
738
739 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
740 void wakeCPU();
741
742 virtual void wakeup();
743
744 /** Gets a free thread id. Use if thread ids change across system. */
745 ThreadID getFreeTid();
746
747 public:
748 /** Returns a pointer to a thread context. */
749 ThreadContext *
750 tcBase(ThreadID tid)
751 {
752 return thread[tid]->getTC();
753 }
754
755 /** The global sequence number counter. */
756 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
757
758 /** Pointer to the checker, which can dynamically verify
759 * instruction results at run time. This can be set to NULL if it
760 * is not being used.
761 */
762 Checker<Impl> *checker;
763
764 /** Pointer to the system. */
765 System *system;
766
767 /** DrainManager to notify when draining has completed. */
768 DrainManager *drainManager;
769
770 /** Pointers to all of the threads in the CPU. */
771 std::vector<Thread *> thread;
772
773 /** Is there a context switch pending? */
774 bool contextSwitch;
775
776 /** Threads Scheduled to Enter CPU */
777 std::list<int> cpuWaitList;
778
779 /** The cycle that the CPU was last running, used for statistics. */
780 Cycles lastRunningCycle;
781
782 /** The cycle that the CPU was last activated by a new thread*/
783 Tick lastActivatedCycle;
784
785 /** Mapping for system thread id to cpu id */
786 std::map<ThreadID, unsigned> threadMap;
787
788 /** Available thread ids in the cpu*/
789 std::vector<ThreadID> tids;
790
791 /** CPU read function, forwards read to LSQ. */
792 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
793 uint8_t *data, int load_idx)
794 {
795 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh,
796 data, load_idx);
797 }
798
799 /** CPU write function, forwards write to LSQ. */
800 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
801 uint8_t *data, int store_idx)
802 {
803 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
804 data, store_idx);
805 }
806
807 /** Used by the fetch unit to get a hold of the instruction port. */
808 virtual CpuPort &getInstPort() { return icachePort; }
809
810 /** Get the dcache port (used to find block size for translations). */
811 virtual CpuPort &getDataPort() { return dcachePort; }
812
813 /** Stat for total number of times the CPU is descheduled. */
814 Stats::Scalar timesIdled;
815 /** Stat for total number of cycles the CPU spends descheduled. */
816 Stats::Scalar idleCycles;
817 /** Stat for total number of cycles the CPU spends descheduled due to a
818 * quiesce operation or waiting for an interrupt. */
819 Stats::Scalar quiesceCycles;
820 /** Stat for the number of committed instructions per thread. */
821 Stats::Vector committedInsts;
822 /** Stat for the number of committed ops (including micro ops) per thread. */
823 Stats::Vector committedOps;
824 /** Stat for the total number of committed instructions. */
825 Stats::Scalar totalCommittedInsts;
826 /** Stat for the CPI per thread. */
827 Stats::Formula cpi;
828 /** Stat for the total CPI. */
829 Stats::Formula totalCpi;
830 /** Stat for the IPC per thread. */
831 Stats::Formula ipc;
832 /** Stat for the total IPC. */
833 Stats::Formula totalIpc;
834
835 //number of integer register file accesses
836 Stats::Scalar intRegfileReads;
837 Stats::Scalar intRegfileWrites;
838 //number of float register file accesses
839 Stats::Scalar fpRegfileReads;
840 Stats::Scalar fpRegfileWrites;
841 //number of misc
842 Stats::Scalar miscRegfileReads;
843 Stats::Scalar miscRegfileWrites;
844};
845
846#endif // __CPU_O3_CPU_HH__
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