1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 * Rick Strong
44 */
45
46#ifndef __CPU_O3_CPU_HH__
47#define __CPU_O3_CPU_HH__
48
49#include <iostream>
50#include <list>
51#include <queue>
52#include <set>
53#include <vector>
54
55#include "arch/types.hh"
56#include "base/statistics.hh"
57#include "config/the_isa.hh"
58#include "config/use_checker.hh"
59#include "cpu/o3/comm.hh"
60#include "cpu/o3/cpu_policy.hh"
61#include "cpu/o3/scoreboard.hh"
62#include "cpu/o3/thread_state.hh"
63#include "cpu/activity.hh"
64#include "cpu/base.hh"
65#include "cpu/simple_thread.hh"
66#include "cpu/timebuf.hh"
67//#include "cpu/o3/thread_context.hh"
68#include "params/DerivO3CPU.hh"
69#include "sim/process.hh"
70
71template <class>
72class Checker;
73class ThreadContext;
74template <class>
75class O3ThreadContext;
76
77class Checkpoint;
78class MemObject;
79class Process;
80
81struct BaseCPUParams;
82
83class BaseO3CPU : public BaseCPU
84{
85 //Stuff that's pretty ISA independent will go here.
86 public:
87 BaseO3CPU(BaseCPUParams *params);
88
89 void regStats();
90};
91
92/**
93 * FullO3CPU class, has each of the stages (fetch through commit)
94 * within it, as well as all of the time buffers between stages. The
95 * tick() function for the CPU is defined here.
96 */
97template <class Impl>
98class FullO3CPU : public BaseO3CPU
99{
100 public:
101 // Typedefs from the Impl here.
102 typedef typename Impl::CPUPol CPUPolicy;
103 typedef typename Impl::DynInstPtr DynInstPtr;
104 typedef typename Impl::O3CPU O3CPU;
105
106 typedef O3ThreadState<Impl> ImplState;
107 typedef O3ThreadState<Impl> Thread;
108
109 typedef typename std::list<DynInstPtr>::iterator ListIt;
110
111 friend class O3ThreadContext<Impl>;
112
113 public:
114 enum Status {
115 Running,
116 Idle,
117 Halted,
118 Blocked,
119 SwitchedOut
120 };
121
122 TheISA::TLB * itb;
123 TheISA::TLB * dtb;
124
125 /** Overall CPU status. */
126 Status _status;
127
128 /** Per-thread status in CPU, used for SMT. */
129 Status _threadStatus[Impl::MaxThreads];
130
131 private:
132
133 /**
134 * IcachePort class for instruction fetch.
135 */
136 class IcachePort : public CpuPort
137 {
138 protected:
139 /** Pointer to fetch. */
140 DefaultFetch<Impl> *fetch;
141
142 public:
143 /** Default constructor. */
144 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
145 : CpuPort(_fetch->name() + "-iport", _cpu), fetch(_fetch)
146 { }
147
148 protected:
149
150 /** Timing version of receive. Handles setting fetch to the
151 * proper status to start fetching. */
152 virtual bool recvTiming(PacketPtr pkt);
153
154 /** Handles doing a retry of a failed fetch. */
155 virtual void recvRetry();
156 };
157
158 /**
159 * DcachePort class for the load/store queue.
160 */
161 class DcachePort : public CpuPort
162 {
163 protected:
164
165 /** Pointer to LSQ. */
166 LSQ<Impl> *lsq;
167
168 public:
169 /** Default constructor. */
170 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
171 : CpuPort(_lsq->name() + "-dport", _cpu), lsq(_lsq)
172 { }
173
174 protected:
175
176 /** Timing version of receive. Handles writing back and
177 * completing the load or store that has returned from
178 * memory. */
179 virtual bool recvTiming(PacketPtr pkt);
180
181 /** Handles doing a retry of the previous send. */
182 virtual void recvRetry();
183
184 /**
185 * As this CPU requires snooping to maintain the load store queue
186 * change the behaviour from the base CPU port.
187 *
188 * @return true since we have to snoop
189 */
190 virtual bool isSnooping()
191 { return true; }
192 };
193
194 class TickEvent : public Event
195 {
196 private:
197 /** Pointer to the CPU. */
198 FullO3CPU<Impl> *cpu;
199
200 public:
201 /** Constructs a tick event. */
202 TickEvent(FullO3CPU<Impl> *c);
203
204 /** Processes a tick event, calling tick() on the CPU. */
205 void process();
206 /** Returns the description of the tick event. */
207 const char *description() const;
208 };
209
210 /** The tick event used for scheduling CPU ticks. */
211 TickEvent tickEvent;
212
213 /** Schedule tick event, regardless of its current state. */
214 void scheduleTickEvent(int delay)
215 {
216 if (tickEvent.squashed())
217 reschedule(tickEvent, nextCycle(curTick() + ticks(delay)));
218 else if (!tickEvent.scheduled())
219 schedule(tickEvent, nextCycle(curTick() + ticks(delay)));
220 }
221
222 /** Unschedule tick event, regardless of its current state. */
223 void unscheduleTickEvent()
224 {
225 if (tickEvent.scheduled())
226 tickEvent.squash();
227 }
228
229 class ActivateThreadEvent : public Event
230 {
231 private:
232 /** Number of Thread to Activate */
233 ThreadID tid;
234
235 /** Pointer to the CPU. */
236 FullO3CPU<Impl> *cpu;
237
238 public:
239 /** Constructs the event. */
240 ActivateThreadEvent();
241
242 /** Initialize Event */
243 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
244
245 /** Processes the event, calling activateThread() on the CPU. */
246 void process();
247
248 /** Returns the description of the event. */
249 const char *description() const;
250 };
251
252 /** Schedule thread to activate , regardless of its current state. */
253 void
254 scheduleActivateThreadEvent(ThreadID tid, int delay)
255 {
256 // Schedule thread to activate, regardless of its current state.
257 if (activateThreadEvent[tid].squashed())
258 reschedule(activateThreadEvent[tid],
259 nextCycle(curTick() + ticks(delay)));
260 else if (!activateThreadEvent[tid].scheduled()) {
261 Tick when = nextCycle(curTick() + ticks(delay));
262
263 // Check if the deallocateEvent is also scheduled, and make
264 // sure they do not happen at same time causing a sleep that
265 // is never woken from.
266 if (deallocateContextEvent[tid].scheduled() &&
267 deallocateContextEvent[tid].when() == when) {
268 when++;
269 }
270
271 schedule(activateThreadEvent[tid], when);
272 }
273 }
274
275 /** Unschedule actiavte thread event, regardless of its current state. */
276 void
277 unscheduleActivateThreadEvent(ThreadID tid)
278 {
279 if (activateThreadEvent[tid].scheduled())
280 activateThreadEvent[tid].squash();
281 }
282
283 /** The tick event used for scheduling CPU ticks. */
284 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
285
286 class DeallocateContextEvent : public Event
287 {
288 private:
289 /** Number of Thread to deactivate */
290 ThreadID tid;
291
292 /** Should the thread be removed from the CPU? */
293 bool remove;
294
295 /** Pointer to the CPU. */
296 FullO3CPU<Impl> *cpu;
297
298 public:
299 /** Constructs the event. */
300 DeallocateContextEvent();
301
302 /** Initialize Event */
303 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
304
305 /** Processes the event, calling activateThread() on the CPU. */
306 void process();
307
308 /** Sets whether the thread should also be removed from the CPU. */
309 void setRemove(bool _remove) { remove = _remove; }
310
311 /** Returns the description of the event. */
312 const char *description() const;
313 };
314
315 /** Schedule cpu to deallocate thread context.*/
316 void
317 scheduleDeallocateContextEvent(ThreadID tid, bool remove, int delay)
318 {
319 // Schedule thread to activate, regardless of its current state.
320 if (deallocateContextEvent[tid].squashed())
321 reschedule(deallocateContextEvent[tid],
322 nextCycle(curTick() + ticks(delay)));
323 else if (!deallocateContextEvent[tid].scheduled())
324 schedule(deallocateContextEvent[tid],
325 nextCycle(curTick() + ticks(delay)));
326 }
327
328 /** Unschedule thread deallocation in CPU */
329 void
330 unscheduleDeallocateContextEvent(ThreadID tid)
331 {
332 if (deallocateContextEvent[tid].scheduled())
333 deallocateContextEvent[tid].squash();
334 }
335
336 /** The tick event used for scheduling CPU ticks. */
337 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
338
339 public:
340 /** Constructs a CPU with the given parameters. */
341 FullO3CPU(DerivO3CPUParams *params);
342 /** Destructor. */
343 ~FullO3CPU();
344
345 /** Registers statistics. */
346 void regStats();
347
348 void demapPage(Addr vaddr, uint64_t asn)
349 {
350 this->itb->demapPage(vaddr, asn);
351 this->dtb->demapPage(vaddr, asn);
352 }
353
354 void demapInstPage(Addr vaddr, uint64_t asn)
355 {
356 this->itb->demapPage(vaddr, asn);
357 }
358
359 void demapDataPage(Addr vaddr, uint64_t asn)
360 {
361 this->dtb->demapPage(vaddr, asn);
362 }
363
| 1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 * Rick Strong
44 */
45
46#ifndef __CPU_O3_CPU_HH__
47#define __CPU_O3_CPU_HH__
48
49#include <iostream>
50#include <list>
51#include <queue>
52#include <set>
53#include <vector>
54
55#include "arch/types.hh"
56#include "base/statistics.hh"
57#include "config/the_isa.hh"
58#include "config/use_checker.hh"
59#include "cpu/o3/comm.hh"
60#include "cpu/o3/cpu_policy.hh"
61#include "cpu/o3/scoreboard.hh"
62#include "cpu/o3/thread_state.hh"
63#include "cpu/activity.hh"
64#include "cpu/base.hh"
65#include "cpu/simple_thread.hh"
66#include "cpu/timebuf.hh"
67//#include "cpu/o3/thread_context.hh"
68#include "params/DerivO3CPU.hh"
69#include "sim/process.hh"
70
71template <class>
72class Checker;
73class ThreadContext;
74template <class>
75class O3ThreadContext;
76
77class Checkpoint;
78class MemObject;
79class Process;
80
81struct BaseCPUParams;
82
83class BaseO3CPU : public BaseCPU
84{
85 //Stuff that's pretty ISA independent will go here.
86 public:
87 BaseO3CPU(BaseCPUParams *params);
88
89 void regStats();
90};
91
92/**
93 * FullO3CPU class, has each of the stages (fetch through commit)
94 * within it, as well as all of the time buffers between stages. The
95 * tick() function for the CPU is defined here.
96 */
97template <class Impl>
98class FullO3CPU : public BaseO3CPU
99{
100 public:
101 // Typedefs from the Impl here.
102 typedef typename Impl::CPUPol CPUPolicy;
103 typedef typename Impl::DynInstPtr DynInstPtr;
104 typedef typename Impl::O3CPU O3CPU;
105
106 typedef O3ThreadState<Impl> ImplState;
107 typedef O3ThreadState<Impl> Thread;
108
109 typedef typename std::list<DynInstPtr>::iterator ListIt;
110
111 friend class O3ThreadContext<Impl>;
112
113 public:
114 enum Status {
115 Running,
116 Idle,
117 Halted,
118 Blocked,
119 SwitchedOut
120 };
121
122 TheISA::TLB * itb;
123 TheISA::TLB * dtb;
124
125 /** Overall CPU status. */
126 Status _status;
127
128 /** Per-thread status in CPU, used for SMT. */
129 Status _threadStatus[Impl::MaxThreads];
130
131 private:
132
133 /**
134 * IcachePort class for instruction fetch.
135 */
136 class IcachePort : public CpuPort
137 {
138 protected:
139 /** Pointer to fetch. */
140 DefaultFetch<Impl> *fetch;
141
142 public:
143 /** Default constructor. */
144 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
145 : CpuPort(_fetch->name() + "-iport", _cpu), fetch(_fetch)
146 { }
147
148 protected:
149
150 /** Timing version of receive. Handles setting fetch to the
151 * proper status to start fetching. */
152 virtual bool recvTiming(PacketPtr pkt);
153
154 /** Handles doing a retry of a failed fetch. */
155 virtual void recvRetry();
156 };
157
158 /**
159 * DcachePort class for the load/store queue.
160 */
161 class DcachePort : public CpuPort
162 {
163 protected:
164
165 /** Pointer to LSQ. */
166 LSQ<Impl> *lsq;
167
168 public:
169 /** Default constructor. */
170 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
171 : CpuPort(_lsq->name() + "-dport", _cpu), lsq(_lsq)
172 { }
173
174 protected:
175
176 /** Timing version of receive. Handles writing back and
177 * completing the load or store that has returned from
178 * memory. */
179 virtual bool recvTiming(PacketPtr pkt);
180
181 /** Handles doing a retry of the previous send. */
182 virtual void recvRetry();
183
184 /**
185 * As this CPU requires snooping to maintain the load store queue
186 * change the behaviour from the base CPU port.
187 *
188 * @return true since we have to snoop
189 */
190 virtual bool isSnooping()
191 { return true; }
192 };
193
194 class TickEvent : public Event
195 {
196 private:
197 /** Pointer to the CPU. */
198 FullO3CPU<Impl> *cpu;
199
200 public:
201 /** Constructs a tick event. */
202 TickEvent(FullO3CPU<Impl> *c);
203
204 /** Processes a tick event, calling tick() on the CPU. */
205 void process();
206 /** Returns the description of the tick event. */
207 const char *description() const;
208 };
209
210 /** The tick event used for scheduling CPU ticks. */
211 TickEvent tickEvent;
212
213 /** Schedule tick event, regardless of its current state. */
214 void scheduleTickEvent(int delay)
215 {
216 if (tickEvent.squashed())
217 reschedule(tickEvent, nextCycle(curTick() + ticks(delay)));
218 else if (!tickEvent.scheduled())
219 schedule(tickEvent, nextCycle(curTick() + ticks(delay)));
220 }
221
222 /** Unschedule tick event, regardless of its current state. */
223 void unscheduleTickEvent()
224 {
225 if (tickEvent.scheduled())
226 tickEvent.squash();
227 }
228
229 class ActivateThreadEvent : public Event
230 {
231 private:
232 /** Number of Thread to Activate */
233 ThreadID tid;
234
235 /** Pointer to the CPU. */
236 FullO3CPU<Impl> *cpu;
237
238 public:
239 /** Constructs the event. */
240 ActivateThreadEvent();
241
242 /** Initialize Event */
243 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
244
245 /** Processes the event, calling activateThread() on the CPU. */
246 void process();
247
248 /** Returns the description of the event. */
249 const char *description() const;
250 };
251
252 /** Schedule thread to activate , regardless of its current state. */
253 void
254 scheduleActivateThreadEvent(ThreadID tid, int delay)
255 {
256 // Schedule thread to activate, regardless of its current state.
257 if (activateThreadEvent[tid].squashed())
258 reschedule(activateThreadEvent[tid],
259 nextCycle(curTick() + ticks(delay)));
260 else if (!activateThreadEvent[tid].scheduled()) {
261 Tick when = nextCycle(curTick() + ticks(delay));
262
263 // Check if the deallocateEvent is also scheduled, and make
264 // sure they do not happen at same time causing a sleep that
265 // is never woken from.
266 if (deallocateContextEvent[tid].scheduled() &&
267 deallocateContextEvent[tid].when() == when) {
268 when++;
269 }
270
271 schedule(activateThreadEvent[tid], when);
272 }
273 }
274
275 /** Unschedule actiavte thread event, regardless of its current state. */
276 void
277 unscheduleActivateThreadEvent(ThreadID tid)
278 {
279 if (activateThreadEvent[tid].scheduled())
280 activateThreadEvent[tid].squash();
281 }
282
283 /** The tick event used for scheduling CPU ticks. */
284 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
285
286 class DeallocateContextEvent : public Event
287 {
288 private:
289 /** Number of Thread to deactivate */
290 ThreadID tid;
291
292 /** Should the thread be removed from the CPU? */
293 bool remove;
294
295 /** Pointer to the CPU. */
296 FullO3CPU<Impl> *cpu;
297
298 public:
299 /** Constructs the event. */
300 DeallocateContextEvent();
301
302 /** Initialize Event */
303 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
304
305 /** Processes the event, calling activateThread() on the CPU. */
306 void process();
307
308 /** Sets whether the thread should also be removed from the CPU. */
309 void setRemove(bool _remove) { remove = _remove; }
310
311 /** Returns the description of the event. */
312 const char *description() const;
313 };
314
315 /** Schedule cpu to deallocate thread context.*/
316 void
317 scheduleDeallocateContextEvent(ThreadID tid, bool remove, int delay)
318 {
319 // Schedule thread to activate, regardless of its current state.
320 if (deallocateContextEvent[tid].squashed())
321 reschedule(deallocateContextEvent[tid],
322 nextCycle(curTick() + ticks(delay)));
323 else if (!deallocateContextEvent[tid].scheduled())
324 schedule(deallocateContextEvent[tid],
325 nextCycle(curTick() + ticks(delay)));
326 }
327
328 /** Unschedule thread deallocation in CPU */
329 void
330 unscheduleDeallocateContextEvent(ThreadID tid)
331 {
332 if (deallocateContextEvent[tid].scheduled())
333 deallocateContextEvent[tid].squash();
334 }
335
336 /** The tick event used for scheduling CPU ticks. */
337 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
338
339 public:
340 /** Constructs a CPU with the given parameters. */
341 FullO3CPU(DerivO3CPUParams *params);
342 /** Destructor. */
343 ~FullO3CPU();
344
345 /** Registers statistics. */
346 void regStats();
347
348 void demapPage(Addr vaddr, uint64_t asn)
349 {
350 this->itb->demapPage(vaddr, asn);
351 this->dtb->demapPage(vaddr, asn);
352 }
353
354 void demapInstPage(Addr vaddr, uint64_t asn)
355 {
356 this->itb->demapPage(vaddr, asn);
357 }
358
359 void demapDataPage(Addr vaddr, uint64_t asn)
360 {
361 this->dtb->demapPage(vaddr, asn);
362 }
363
|
364 /** Returns a specific port. */
365 Port *getPort(const std::string &if_name, int idx);
366
| |
367 /** Ticks CPU, calling tick() on each stage, and checking the overall
368 * activity to see if the CPU should deschedule itself.
369 */
370 void tick();
371
372 /** Initialize the CPU */
373 void init();
374
375 /** Returns the Number of Active Threads in the CPU */
376 int numActiveThreads()
377 { return activeThreads.size(); }
378
379 /** Add Thread to Active Threads List */
380 void activateThread(ThreadID tid);
381
382 /** Remove Thread from Active Threads List */
383 void deactivateThread(ThreadID tid);
384
385 /** Setup CPU to insert a thread's context */
386 void insertThread(ThreadID tid);
387
388 /** Remove all of a thread's context from CPU */
389 void removeThread(ThreadID tid);
390
391 /** Count the Total Instructions Committed in the CPU. */
392 virtual Counter totalInsts() const;
393
394 /** Count the Total Ops (including micro ops) committed in the CPU. */
395 virtual Counter totalOps() const;
396
397 /** Add Thread to Active Threads List. */
398 void activateContext(ThreadID tid, int delay);
399
400 /** Remove Thread from Active Threads List */
401 void suspendContext(ThreadID tid);
402
403 /** Remove Thread from Active Threads List &&
404 * Possibly Remove Thread Context from CPU.
405 */
406 bool scheduleDeallocateContext(ThreadID tid, bool remove, int delay = 1);
407
408 /** Remove Thread from Active Threads List &&
409 * Remove Thread Context from CPU.
410 */
411 void haltContext(ThreadID tid);
412
413 /** Activate a Thread When CPU Resources are Available. */
414 void activateWhenReady(ThreadID tid);
415
416 /** Add or Remove a Thread Context in the CPU. */
417 void doContextSwitch();
418
419 /** Update The Order In Which We Process Threads. */
420 void updateThreadPriority();
421
422 /** Serialize state. */
423 virtual void serialize(std::ostream &os);
424
425 /** Unserialize from a checkpoint. */
426 virtual void unserialize(Checkpoint *cp, const std::string §ion);
427
428 public:
429 /** Executes a syscall.
430 * @todo: Determine if this needs to be virtual.
431 */
432 void syscall(int64_t callnum, ThreadID tid);
433
434 /** Starts draining the CPU's pipeline of all instructions in
435 * order to stop all memory accesses. */
436 virtual unsigned int drain(Event *drain_event);
437
438 /** Resumes execution after a drain. */
439 virtual void resume();
440
441 /** Signals to this CPU that a stage has completed switching out. */
442 void signalDrained();
443
444 /** Switches out this CPU. */
445 virtual void switchOut();
446
447 /** Takes over from another CPU. */
448 virtual void takeOverFrom(BaseCPU *oldCPU);
449
450 /** Get the current instruction sequence number, and increment it. */
451 InstSeqNum getAndIncrementInstSeq()
452 { return globalSeqNum++; }
453
454 /** Traps to handle given fault. */
455 void trap(Fault fault, ThreadID tid, StaticInstPtr inst);
456
457 /** HW return from error interrupt. */
458 Fault hwrei(ThreadID tid);
459
460 bool simPalCheck(int palFunc, ThreadID tid);
461
462 /** Returns the Fault for any valid interrupt. */
463 Fault getInterrupts();
464
465 /** Processes any an interrupt fault. */
466 void processInterrupts(Fault interrupt);
467
468 /** Halts the CPU. */
469 void halt() { panic("Halt not implemented!\n"); }
470
471 /** Check if this address is a valid instruction address. */
472 bool validInstAddr(Addr addr) { return true; }
473
474 /** Check if this address is a valid data address. */
475 bool validDataAddr(Addr addr) { return true; }
476
477 /** Register accessors. Index refers to the physical register index. */
478
479 /** Reads a miscellaneous register. */
480 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
481
482 /** Reads a misc. register, including any side effects the read
483 * might have as defined by the architecture.
484 */
485 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
486
487 /** Sets a miscellaneous register. */
488 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
489 ThreadID tid);
490
491 /** Sets a misc. register, including any side effects the write
492 * might have as defined by the architecture.
493 */
494 void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
495 ThreadID tid);
496
497 uint64_t readIntReg(int reg_idx);
498
499 TheISA::FloatReg readFloatReg(int reg_idx);
500
501 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
502
503 void setIntReg(int reg_idx, uint64_t val);
504
505 void setFloatReg(int reg_idx, TheISA::FloatReg val);
506
507 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
508
509 uint64_t readArchIntReg(int reg_idx, ThreadID tid);
510
511 float readArchFloatReg(int reg_idx, ThreadID tid);
512
513 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
514
515 /** Architectural register accessors. Looks up in the commit
516 * rename table to obtain the true physical index of the
517 * architected register first, then accesses that physical
518 * register.
519 */
520 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
521
522 void setArchFloatReg(int reg_idx, float val, ThreadID tid);
523
524 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
525
526 /** Sets the commit PC state of a specific thread. */
527 void pcState(const TheISA::PCState &newPCState, ThreadID tid);
528
529 /** Reads the commit PC state of a specific thread. */
530 TheISA::PCState pcState(ThreadID tid);
531
532 /** Reads the commit PC of a specific thread. */
533 Addr instAddr(ThreadID tid);
534
535 /** Reads the commit micro PC of a specific thread. */
536 MicroPC microPC(ThreadID tid);
537
538 /** Reads the next PC of a specific thread. */
539 Addr nextInstAddr(ThreadID tid);
540
541 /** Initiates a squash of all in-flight instructions for a given
542 * thread. The source of the squash is an external update of
543 * state through the TC.
544 */
545 void squashFromTC(ThreadID tid);
546
547 /** Function to add instruction onto the head of the list of the
548 * instructions. Used when new instructions are fetched.
549 */
550 ListIt addInst(DynInstPtr &inst);
551
552 /** Function to tell the CPU that an instruction has completed. */
553 void instDone(ThreadID tid, DynInstPtr &inst);
554
555 /** Remove an instruction from the front end of the list. There's
556 * no restriction on location of the instruction.
557 */
558 void removeFrontInst(DynInstPtr &inst);
559
560 /** Remove all instructions that are not currently in the ROB.
561 * There's also an option to not squash delay slot instructions.*/
562 void removeInstsNotInROB(ThreadID tid);
563
564 /** Remove all instructions younger than the given sequence number. */
565 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
566
567 /** Removes the instruction pointed to by the iterator. */
568 inline void squashInstIt(const ListIt &instIt, ThreadID tid);
569
570 /** Cleans up all instructions on the remove list. */
571 void cleanUpRemovedInsts();
572
573 /** Debug function to print all instructions on the list. */
574 void dumpInsts();
575
576 public:
577#ifndef NDEBUG
578 /** Count of total number of dynamic instructions in flight. */
579 int instcount;
580#endif
581
582 /** List of all the instructions in flight. */
583 std::list<DynInstPtr> instList;
584
585 /** List of all the instructions that will be removed at the end of this
586 * cycle.
587 */
588 std::queue<ListIt> removeList;
589
590#ifdef DEBUG
591 /** Debug structure to keep track of the sequence numbers still in
592 * flight.
593 */
594 std::set<InstSeqNum> snList;
595#endif
596
597 /** Records if instructions need to be removed this cycle due to
598 * being retired or squashed.
599 */
600 bool removeInstsThisCycle;
601
602 protected:
603 /** The fetch stage. */
604 typename CPUPolicy::Fetch fetch;
605
606 /** The decode stage. */
607 typename CPUPolicy::Decode decode;
608
609 /** The dispatch stage. */
610 typename CPUPolicy::Rename rename;
611
612 /** The issue/execute/writeback stages. */
613 typename CPUPolicy::IEW iew;
614
615 /** The commit stage. */
616 typename CPUPolicy::Commit commit;
617
618 /** The register file. */
619 typename CPUPolicy::RegFile regFile;
620
621 /** The free list. */
622 typename CPUPolicy::FreeList freeList;
623
624 /** The rename map. */
625 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
626
627 /** The commit rename map. */
628 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
629
630 /** The re-order buffer. */
631 typename CPUPolicy::ROB rob;
632
633 /** Active Threads List */
634 std::list<ThreadID> activeThreads;
635
636 /** Integer Register Scoreboard */
637 Scoreboard scoreboard;
638
639 TheISA::ISA isa[Impl::MaxThreads];
640
641 /** Instruction port. Note that it has to appear after the fetch stage. */
642 IcachePort icachePort;
643
644 /** Data port. Note that it has to appear after the iew stages */
645 DcachePort dcachePort;
646
647 public:
648 /** Enum to give each stage a specific index, so when calling
649 * activateStage() or deactivateStage(), they can specify which stage
650 * is being activated/deactivated.
651 */
652 enum StageIdx {
653 FetchIdx,
654 DecodeIdx,
655 RenameIdx,
656 IEWIdx,
657 CommitIdx,
658 NumStages };
659
660 /** Typedefs from the Impl to get the structs that each of the
661 * time buffers should use.
662 */
663 typedef typename CPUPolicy::TimeStruct TimeStruct;
664
665 typedef typename CPUPolicy::FetchStruct FetchStruct;
666
667 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
668
669 typedef typename CPUPolicy::RenameStruct RenameStruct;
670
671 typedef typename CPUPolicy::IEWStruct IEWStruct;
672
673 /** The main time buffer to do backwards communication. */
674 TimeBuffer<TimeStruct> timeBuffer;
675
676 /** The fetch stage's instruction queue. */
677 TimeBuffer<FetchStruct> fetchQueue;
678
679 /** The decode stage's instruction queue. */
680 TimeBuffer<DecodeStruct> decodeQueue;
681
682 /** The rename stage's instruction queue. */
683 TimeBuffer<RenameStruct> renameQueue;
684
685 /** The IEW stage's instruction queue. */
686 TimeBuffer<IEWStruct> iewQueue;
687
688 private:
689 /** The activity recorder; used to tell if the CPU has any
690 * activity remaining or if it can go to idle and deschedule
691 * itself.
692 */
693 ActivityRecorder activityRec;
694
695 public:
696 /** Records that there was time buffer activity this cycle. */
697 void activityThisCycle() { activityRec.activity(); }
698
699 /** Changes a stage's status to active within the activity recorder. */
700 void activateStage(const StageIdx idx)
701 { activityRec.activateStage(idx); }
702
703 /** Changes a stage's status to inactive within the activity recorder. */
704 void deactivateStage(const StageIdx idx)
705 { activityRec.deactivateStage(idx); }
706
707 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
708 void wakeCPU();
709
710 virtual void wakeup();
711
712 /** Gets a free thread id. Use if thread ids change across system. */
713 ThreadID getFreeTid();
714
715 public:
716 /** Returns a pointer to a thread context. */
717 ThreadContext *
718 tcBase(ThreadID tid)
719 {
720 return thread[tid]->getTC();
721 }
722
723 /** The global sequence number counter. */
724 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
725
726#if USE_CHECKER
727 /** Pointer to the checker, which can dynamically verify
728 * instruction results at run time. This can be set to NULL if it
729 * is not being used.
730 */
731 Checker<Impl> *checker;
732#endif
733
734 /** Pointer to the system. */
735 System *system;
736
737 /** Event to call process() on once draining has completed. */
738 Event *drainEvent;
739
740 /** Counter of how many stages have completed draining. */
741 int drainCount;
742
743 /** Pointers to all of the threads in the CPU. */
744 std::vector<Thread *> thread;
745
746 /** Whether or not the CPU should defer its registration. */
747 bool deferRegistration;
748
749 /** Is there a context switch pending? */
750 bool contextSwitch;
751
752 /** Threads Scheduled to Enter CPU */
753 std::list<int> cpuWaitList;
754
755 /** The cycle that the CPU was last running, used for statistics. */
756 Tick lastRunningCycle;
757
758 /** The cycle that the CPU was last activated by a new thread*/
759 Tick lastActivatedCycle;
760
761 /** Mapping for system thread id to cpu id */
762 std::map<ThreadID, unsigned> threadMap;
763
764 /** Available thread ids in the cpu*/
765 std::vector<ThreadID> tids;
766
767 /** CPU read function, forwards read to LSQ. */
768 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
769 uint8_t *data, int load_idx)
770 {
771 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh,
772 data, load_idx);
773 }
774
775 /** CPU write function, forwards write to LSQ. */
776 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
777 uint8_t *data, int store_idx)
778 {
779 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
780 data, store_idx);
781 }
782
783 /** Used by the fetch unit to get a hold of the instruction port. */
| 364 /** Ticks CPU, calling tick() on each stage, and checking the overall
365 * activity to see if the CPU should deschedule itself.
366 */
367 void tick();
368
369 /** Initialize the CPU */
370 void init();
371
372 /** Returns the Number of Active Threads in the CPU */
373 int numActiveThreads()
374 { return activeThreads.size(); }
375
376 /** Add Thread to Active Threads List */
377 void activateThread(ThreadID tid);
378
379 /** Remove Thread from Active Threads List */
380 void deactivateThread(ThreadID tid);
381
382 /** Setup CPU to insert a thread's context */
383 void insertThread(ThreadID tid);
384
385 /** Remove all of a thread's context from CPU */
386 void removeThread(ThreadID tid);
387
388 /** Count the Total Instructions Committed in the CPU. */
389 virtual Counter totalInsts() const;
390
391 /** Count the Total Ops (including micro ops) committed in the CPU. */
392 virtual Counter totalOps() const;
393
394 /** Add Thread to Active Threads List. */
395 void activateContext(ThreadID tid, int delay);
396
397 /** Remove Thread from Active Threads List */
398 void suspendContext(ThreadID tid);
399
400 /** Remove Thread from Active Threads List &&
401 * Possibly Remove Thread Context from CPU.
402 */
403 bool scheduleDeallocateContext(ThreadID tid, bool remove, int delay = 1);
404
405 /** Remove Thread from Active Threads List &&
406 * Remove Thread Context from CPU.
407 */
408 void haltContext(ThreadID tid);
409
410 /** Activate a Thread When CPU Resources are Available. */
411 void activateWhenReady(ThreadID tid);
412
413 /** Add or Remove a Thread Context in the CPU. */
414 void doContextSwitch();
415
416 /** Update The Order In Which We Process Threads. */
417 void updateThreadPriority();
418
419 /** Serialize state. */
420 virtual void serialize(std::ostream &os);
421
422 /** Unserialize from a checkpoint. */
423 virtual void unserialize(Checkpoint *cp, const std::string §ion);
424
425 public:
426 /** Executes a syscall.
427 * @todo: Determine if this needs to be virtual.
428 */
429 void syscall(int64_t callnum, ThreadID tid);
430
431 /** Starts draining the CPU's pipeline of all instructions in
432 * order to stop all memory accesses. */
433 virtual unsigned int drain(Event *drain_event);
434
435 /** Resumes execution after a drain. */
436 virtual void resume();
437
438 /** Signals to this CPU that a stage has completed switching out. */
439 void signalDrained();
440
441 /** Switches out this CPU. */
442 virtual void switchOut();
443
444 /** Takes over from another CPU. */
445 virtual void takeOverFrom(BaseCPU *oldCPU);
446
447 /** Get the current instruction sequence number, and increment it. */
448 InstSeqNum getAndIncrementInstSeq()
449 { return globalSeqNum++; }
450
451 /** Traps to handle given fault. */
452 void trap(Fault fault, ThreadID tid, StaticInstPtr inst);
453
454 /** HW return from error interrupt. */
455 Fault hwrei(ThreadID tid);
456
457 bool simPalCheck(int palFunc, ThreadID tid);
458
459 /** Returns the Fault for any valid interrupt. */
460 Fault getInterrupts();
461
462 /** Processes any an interrupt fault. */
463 void processInterrupts(Fault interrupt);
464
465 /** Halts the CPU. */
466 void halt() { panic("Halt not implemented!\n"); }
467
468 /** Check if this address is a valid instruction address. */
469 bool validInstAddr(Addr addr) { return true; }
470
471 /** Check if this address is a valid data address. */
472 bool validDataAddr(Addr addr) { return true; }
473
474 /** Register accessors. Index refers to the physical register index. */
475
476 /** Reads a miscellaneous register. */
477 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
478
479 /** Reads a misc. register, including any side effects the read
480 * might have as defined by the architecture.
481 */
482 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
483
484 /** Sets a miscellaneous register. */
485 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
486 ThreadID tid);
487
488 /** Sets a misc. register, including any side effects the write
489 * might have as defined by the architecture.
490 */
491 void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
492 ThreadID tid);
493
494 uint64_t readIntReg(int reg_idx);
495
496 TheISA::FloatReg readFloatReg(int reg_idx);
497
498 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
499
500 void setIntReg(int reg_idx, uint64_t val);
501
502 void setFloatReg(int reg_idx, TheISA::FloatReg val);
503
504 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
505
506 uint64_t readArchIntReg(int reg_idx, ThreadID tid);
507
508 float readArchFloatReg(int reg_idx, ThreadID tid);
509
510 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
511
512 /** Architectural register accessors. Looks up in the commit
513 * rename table to obtain the true physical index of the
514 * architected register first, then accesses that physical
515 * register.
516 */
517 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
518
519 void setArchFloatReg(int reg_idx, float val, ThreadID tid);
520
521 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
522
523 /** Sets the commit PC state of a specific thread. */
524 void pcState(const TheISA::PCState &newPCState, ThreadID tid);
525
526 /** Reads the commit PC state of a specific thread. */
527 TheISA::PCState pcState(ThreadID tid);
528
529 /** Reads the commit PC of a specific thread. */
530 Addr instAddr(ThreadID tid);
531
532 /** Reads the commit micro PC of a specific thread. */
533 MicroPC microPC(ThreadID tid);
534
535 /** Reads the next PC of a specific thread. */
536 Addr nextInstAddr(ThreadID tid);
537
538 /** Initiates a squash of all in-flight instructions for a given
539 * thread. The source of the squash is an external update of
540 * state through the TC.
541 */
542 void squashFromTC(ThreadID tid);
543
544 /** Function to add instruction onto the head of the list of the
545 * instructions. Used when new instructions are fetched.
546 */
547 ListIt addInst(DynInstPtr &inst);
548
549 /** Function to tell the CPU that an instruction has completed. */
550 void instDone(ThreadID tid, DynInstPtr &inst);
551
552 /** Remove an instruction from the front end of the list. There's
553 * no restriction on location of the instruction.
554 */
555 void removeFrontInst(DynInstPtr &inst);
556
557 /** Remove all instructions that are not currently in the ROB.
558 * There's also an option to not squash delay slot instructions.*/
559 void removeInstsNotInROB(ThreadID tid);
560
561 /** Remove all instructions younger than the given sequence number. */
562 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
563
564 /** Removes the instruction pointed to by the iterator. */
565 inline void squashInstIt(const ListIt &instIt, ThreadID tid);
566
567 /** Cleans up all instructions on the remove list. */
568 void cleanUpRemovedInsts();
569
570 /** Debug function to print all instructions on the list. */
571 void dumpInsts();
572
573 public:
574#ifndef NDEBUG
575 /** Count of total number of dynamic instructions in flight. */
576 int instcount;
577#endif
578
579 /** List of all the instructions in flight. */
580 std::list<DynInstPtr> instList;
581
582 /** List of all the instructions that will be removed at the end of this
583 * cycle.
584 */
585 std::queue<ListIt> removeList;
586
587#ifdef DEBUG
588 /** Debug structure to keep track of the sequence numbers still in
589 * flight.
590 */
591 std::set<InstSeqNum> snList;
592#endif
593
594 /** Records if instructions need to be removed this cycle due to
595 * being retired or squashed.
596 */
597 bool removeInstsThisCycle;
598
599 protected:
600 /** The fetch stage. */
601 typename CPUPolicy::Fetch fetch;
602
603 /** The decode stage. */
604 typename CPUPolicy::Decode decode;
605
606 /** The dispatch stage. */
607 typename CPUPolicy::Rename rename;
608
609 /** The issue/execute/writeback stages. */
610 typename CPUPolicy::IEW iew;
611
612 /** The commit stage. */
613 typename CPUPolicy::Commit commit;
614
615 /** The register file. */
616 typename CPUPolicy::RegFile regFile;
617
618 /** The free list. */
619 typename CPUPolicy::FreeList freeList;
620
621 /** The rename map. */
622 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
623
624 /** The commit rename map. */
625 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
626
627 /** The re-order buffer. */
628 typename CPUPolicy::ROB rob;
629
630 /** Active Threads List */
631 std::list<ThreadID> activeThreads;
632
633 /** Integer Register Scoreboard */
634 Scoreboard scoreboard;
635
636 TheISA::ISA isa[Impl::MaxThreads];
637
638 /** Instruction port. Note that it has to appear after the fetch stage. */
639 IcachePort icachePort;
640
641 /** Data port. Note that it has to appear after the iew stages */
642 DcachePort dcachePort;
643
644 public:
645 /** Enum to give each stage a specific index, so when calling
646 * activateStage() or deactivateStage(), they can specify which stage
647 * is being activated/deactivated.
648 */
649 enum StageIdx {
650 FetchIdx,
651 DecodeIdx,
652 RenameIdx,
653 IEWIdx,
654 CommitIdx,
655 NumStages };
656
657 /** Typedefs from the Impl to get the structs that each of the
658 * time buffers should use.
659 */
660 typedef typename CPUPolicy::TimeStruct TimeStruct;
661
662 typedef typename CPUPolicy::FetchStruct FetchStruct;
663
664 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
665
666 typedef typename CPUPolicy::RenameStruct RenameStruct;
667
668 typedef typename CPUPolicy::IEWStruct IEWStruct;
669
670 /** The main time buffer to do backwards communication. */
671 TimeBuffer<TimeStruct> timeBuffer;
672
673 /** The fetch stage's instruction queue. */
674 TimeBuffer<FetchStruct> fetchQueue;
675
676 /** The decode stage's instruction queue. */
677 TimeBuffer<DecodeStruct> decodeQueue;
678
679 /** The rename stage's instruction queue. */
680 TimeBuffer<RenameStruct> renameQueue;
681
682 /** The IEW stage's instruction queue. */
683 TimeBuffer<IEWStruct> iewQueue;
684
685 private:
686 /** The activity recorder; used to tell if the CPU has any
687 * activity remaining or if it can go to idle and deschedule
688 * itself.
689 */
690 ActivityRecorder activityRec;
691
692 public:
693 /** Records that there was time buffer activity this cycle. */
694 void activityThisCycle() { activityRec.activity(); }
695
696 /** Changes a stage's status to active within the activity recorder. */
697 void activateStage(const StageIdx idx)
698 { activityRec.activateStage(idx); }
699
700 /** Changes a stage's status to inactive within the activity recorder. */
701 void deactivateStage(const StageIdx idx)
702 { activityRec.deactivateStage(idx); }
703
704 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
705 void wakeCPU();
706
707 virtual void wakeup();
708
709 /** Gets a free thread id. Use if thread ids change across system. */
710 ThreadID getFreeTid();
711
712 public:
713 /** Returns a pointer to a thread context. */
714 ThreadContext *
715 tcBase(ThreadID tid)
716 {
717 return thread[tid]->getTC();
718 }
719
720 /** The global sequence number counter. */
721 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
722
723#if USE_CHECKER
724 /** Pointer to the checker, which can dynamically verify
725 * instruction results at run time. This can be set to NULL if it
726 * is not being used.
727 */
728 Checker<Impl> *checker;
729#endif
730
731 /** Pointer to the system. */
732 System *system;
733
734 /** Event to call process() on once draining has completed. */
735 Event *drainEvent;
736
737 /** Counter of how many stages have completed draining. */
738 int drainCount;
739
740 /** Pointers to all of the threads in the CPU. */
741 std::vector<Thread *> thread;
742
743 /** Whether or not the CPU should defer its registration. */
744 bool deferRegistration;
745
746 /** Is there a context switch pending? */
747 bool contextSwitch;
748
749 /** Threads Scheduled to Enter CPU */
750 std::list<int> cpuWaitList;
751
752 /** The cycle that the CPU was last running, used for statistics. */
753 Tick lastRunningCycle;
754
755 /** The cycle that the CPU was last activated by a new thread*/
756 Tick lastActivatedCycle;
757
758 /** Mapping for system thread id to cpu id */
759 std::map<ThreadID, unsigned> threadMap;
760
761 /** Available thread ids in the cpu*/
762 std::vector<ThreadID> tids;
763
764 /** CPU read function, forwards read to LSQ. */
765 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
766 uint8_t *data, int load_idx)
767 {
768 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh,
769 data, load_idx);
770 }
771
772 /** CPU write function, forwards write to LSQ. */
773 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
774 uint8_t *data, int store_idx)
775 {
776 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
777 data, store_idx);
778 }
779
780 /** Used by the fetch unit to get a hold of the instruction port. */
|
784 Port* getIcachePort() { return &icachePort; }
| 781 virtual CpuPort &getInstPort() { return icachePort; }
|
785
786 /** Get the dcache port (used to find block size for translations). */
| 782
783 /** Get the dcache port (used to find block size for translations). */
|
787 Port* getDcachePort() { return &dcachePort; }
| 784 virtual CpuPort &getDataPort() { return dcachePort; }
|
788
789 Addr lockAddr;
790
791 /** Temporary fix for the lock flag, works in the UP case. */
792 bool lockFlag;
793
794 /** Stat for total number of times the CPU is descheduled. */
795 Stats::Scalar timesIdled;
796 /** Stat for total number of cycles the CPU spends descheduled. */
797 Stats::Scalar idleCycles;
798 /** Stat for total number of cycles the CPU spends descheduled due to a
799 * quiesce operation or waiting for an interrupt. */
800 Stats::Scalar quiesceCycles;
801 /** Stat for the number of committed instructions per thread. */
802 Stats::Vector committedInsts;
803 /** Stat for the number of committed ops (including micro ops) per thread. */
804 Stats::Vector committedOps;
805 /** Stat for the total number of committed instructions. */
806 Stats::Scalar totalCommittedInsts;
807 /** Stat for the CPI per thread. */
808 Stats::Formula cpi;
809 /** Stat for the total CPI. */
810 Stats::Formula totalCpi;
811 /** Stat for the IPC per thread. */
812 Stats::Formula ipc;
813 /** Stat for the total IPC. */
814 Stats::Formula totalIpc;
815
816 //number of integer register file accesses
817 Stats::Scalar intRegfileReads;
818 Stats::Scalar intRegfileWrites;
819 //number of float register file accesses
820 Stats::Scalar fpRegfileReads;
821 Stats::Scalar fpRegfileWrites;
822 //number of misc
823 Stats::Scalar miscRegfileReads;
824 Stats::Scalar miscRegfileWrites;
825};
826
827#endif // __CPU_O3_CPU_HH__
| 785
786 Addr lockAddr;
787
788 /** Temporary fix for the lock flag, works in the UP case. */
789 bool lockFlag;
790
791 /** Stat for total number of times the CPU is descheduled. */
792 Stats::Scalar timesIdled;
793 /** Stat for total number of cycles the CPU spends descheduled. */
794 Stats::Scalar idleCycles;
795 /** Stat for total number of cycles the CPU spends descheduled due to a
796 * quiesce operation or waiting for an interrupt. */
797 Stats::Scalar quiesceCycles;
798 /** Stat for the number of committed instructions per thread. */
799 Stats::Vector committedInsts;
800 /** Stat for the number of committed ops (including micro ops) per thread. */
801 Stats::Vector committedOps;
802 /** Stat for the total number of committed instructions. */
803 Stats::Scalar totalCommittedInsts;
804 /** Stat for the CPI per thread. */
805 Stats::Formula cpi;
806 /** Stat for the total CPI. */
807 Stats::Formula totalCpi;
808 /** Stat for the IPC per thread. */
809 Stats::Formula ipc;
810 /** Stat for the total IPC. */
811 Stats::Formula totalIpc;
812
813 //number of integer register file accesses
814 Stats::Scalar intRegfileReads;
815 Stats::Scalar intRegfileWrites;
816 //number of float register file accesses
817 Stats::Scalar fpRegfileReads;
818 Stats::Scalar fpRegfileWrites;
819 //number of misc
820 Stats::Scalar miscRegfileReads;
821 Stats::Scalar miscRegfileWrites;
822};
823
824#endif // __CPU_O3_CPU_HH__
|