1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * Copyright (c) 2011 Regents of the University of California 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Kevin Lim 30 * Korey Sewell 31 * Rick Strong 32 */ 33 34#ifndef __CPU_O3_CPU_HH__ 35#define __CPU_O3_CPU_HH__ 36 37#include <iostream> 38#include <list> 39#include <queue> 40#include <set> 41#include <vector> 42 43#include "arch/types.hh" 44#include "base/statistics.hh" 45#include "config/the_isa.hh" 46#include "config/use_checker.hh" 47#include "cpu/o3/comm.hh" 48#include "cpu/o3/cpu_policy.hh" 49#include "cpu/o3/scoreboard.hh" 50#include "cpu/o3/thread_state.hh" 51#include "cpu/activity.hh" 52#include "cpu/base.hh" 53#include "cpu/simple_thread.hh" 54#include "cpu/timebuf.hh" 55//#include "cpu/o3/thread_context.hh" 56#include "params/DerivO3CPU.hh" 57#include "sim/process.hh" 58 59template <class> 60class Checker; 61class ThreadContext; 62template <class> 63class O3ThreadContext; 64 65class Checkpoint; 66class MemObject; 67class Process; 68 69class BaseCPUParams; 70 71class BaseO3CPU : public BaseCPU 72{ 73 //Stuff that's pretty ISA independent will go here. 74 public: 75 BaseO3CPU(BaseCPUParams *params); 76 77 void regStats(); 78}; 79 80/** 81 * FullO3CPU class, has each of the stages (fetch through commit) 82 * within it, as well as all of the time buffers between stages. The 83 * tick() function for the CPU is defined here. 84 */ 85template <class Impl> 86class FullO3CPU : public BaseO3CPU 87{ 88 public: 89 // Typedefs from the Impl here. 90 typedef typename Impl::CPUPol CPUPolicy; 91 typedef typename Impl::DynInstPtr DynInstPtr; 92 typedef typename Impl::O3CPU O3CPU; 93 94 typedef O3ThreadState<Impl> ImplState; 95 typedef O3ThreadState<Impl> Thread; 96 97 typedef typename std::list<DynInstPtr>::iterator ListIt; 98 99 friend class O3ThreadContext<Impl>; 100 101 public: 102 enum Status { 103 Running, 104 Idle, 105 Halted, 106 Blocked, 107 SwitchedOut 108 }; 109 110 TheISA::TLB * itb; 111 TheISA::TLB * dtb; 112 113 /** Overall CPU status. */ 114 Status _status; 115 116 /** Per-thread status in CPU, used for SMT. */ 117 Status _threadStatus[Impl::MaxThreads]; 118 119 private: 120 class TickEvent : public Event 121 { 122 private: 123 /** Pointer to the CPU. */ 124 FullO3CPU<Impl> *cpu; 125 126 public: 127 /** Constructs a tick event. */ 128 TickEvent(FullO3CPU<Impl> *c); 129 130 /** Processes a tick event, calling tick() on the CPU. */ 131 void process(); 132 /** Returns the description of the tick event. */ 133 const char *description() const; 134 }; 135 136 /** The tick event used for scheduling CPU ticks. */ 137 TickEvent tickEvent; 138 139 /** Schedule tick event, regardless of its current state. */ 140 void scheduleTickEvent(int delay) 141 { 142 if (tickEvent.squashed()) 143 reschedule(tickEvent, nextCycle(curTick() + ticks(delay))); 144 else if (!tickEvent.scheduled()) 145 schedule(tickEvent, nextCycle(curTick() + ticks(delay))); 146 } 147 148 /** Unschedule tick event, regardless of its current state. */ 149 void unscheduleTickEvent() 150 { 151 if (tickEvent.scheduled()) 152 tickEvent.squash(); 153 } 154 155 class ActivateThreadEvent : public Event 156 { 157 private: 158 /** Number of Thread to Activate */ 159 ThreadID tid; 160 161 /** Pointer to the CPU. */ 162 FullO3CPU<Impl> *cpu; 163 164 public: 165 /** Constructs the event. */ 166 ActivateThreadEvent(); 167 168 /** Initialize Event */ 169 void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 170 171 /** Processes the event, calling activateThread() on the CPU. */ 172 void process(); 173 174 /** Returns the description of the event. */ 175 const char *description() const; 176 }; 177 178 /** Schedule thread to activate , regardless of its current state. */ 179 void 180 scheduleActivateThreadEvent(ThreadID tid, int delay) 181 { 182 // Schedule thread to activate, regardless of its current state. 183 if (activateThreadEvent[tid].squashed()) 184 reschedule(activateThreadEvent[tid], 185 nextCycle(curTick() + ticks(delay))); 186 else if (!activateThreadEvent[tid].scheduled()) { 187 Tick when = nextCycle(curTick() + ticks(delay)); 188 189 // Check if the deallocateEvent is also scheduled, and make 190 // sure they do not happen at same time causing a sleep that 191 // is never woken from. 192 if (deallocateContextEvent[tid].scheduled() && 193 deallocateContextEvent[tid].when() == when) { 194 when++; 195 } 196 197 schedule(activateThreadEvent[tid], when); 198 } 199 } 200 201 /** Unschedule actiavte thread event, regardless of its current state. */ 202 void 203 unscheduleActivateThreadEvent(ThreadID tid) 204 { 205 if (activateThreadEvent[tid].scheduled()) 206 activateThreadEvent[tid].squash(); 207 } 208 209 /** The tick event used for scheduling CPU ticks. */ 210 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 211 212 class DeallocateContextEvent : public Event 213 { 214 private: 215 /** Number of Thread to deactivate */ 216 ThreadID tid; 217 218 /** Should the thread be removed from the CPU? */ 219 bool remove; 220 221 /** Pointer to the CPU. */ 222 FullO3CPU<Impl> *cpu; 223 224 public: 225 /** Constructs the event. */ 226 DeallocateContextEvent(); 227 228 /** Initialize Event */ 229 void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 230 231 /** Processes the event, calling activateThread() on the CPU. */ 232 void process(); 233 234 /** Sets whether the thread should also be removed from the CPU. */ 235 void setRemove(bool _remove) { remove = _remove; } 236 237 /** Returns the description of the event. */ 238 const char *description() const; 239 }; 240 241 /** Schedule cpu to deallocate thread context.*/ 242 void 243 scheduleDeallocateContextEvent(ThreadID tid, bool remove, int delay) 244 { 245 // Schedule thread to activate, regardless of its current state. 246 if (deallocateContextEvent[tid].squashed()) 247 reschedule(deallocateContextEvent[tid], 248 nextCycle(curTick() + ticks(delay))); 249 else if (!deallocateContextEvent[tid].scheduled()) 250 schedule(deallocateContextEvent[tid], 251 nextCycle(curTick() + ticks(delay))); 252 } 253 254 /** Unschedule thread deallocation in CPU */ 255 void 256 unscheduleDeallocateContextEvent(ThreadID tid) 257 { 258 if (deallocateContextEvent[tid].scheduled()) 259 deallocateContextEvent[tid].squash(); 260 } 261 262 /** The tick event used for scheduling CPU ticks. */ 263 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads]; 264 265 public: 266 /** Constructs a CPU with the given parameters. */ 267 FullO3CPU(DerivO3CPUParams *params); 268 /** Destructor. */ 269 ~FullO3CPU(); 270 271 /** Registers statistics. */ 272 void regStats(); 273 274 void demapPage(Addr vaddr, uint64_t asn) 275 { 276 this->itb->demapPage(vaddr, asn); 277 this->dtb->demapPage(vaddr, asn); 278 } 279 280 void demapInstPage(Addr vaddr, uint64_t asn) 281 { 282 this->itb->demapPage(vaddr, asn); 283 } 284 285 void demapDataPage(Addr vaddr, uint64_t asn) 286 { 287 this->dtb->demapPage(vaddr, asn); 288 } 289 290 /** Returns a specific port. */ 291 Port *getPort(const std::string &if_name, int idx); 292 293 /** Ticks CPU, calling tick() on each stage, and checking the overall 294 * activity to see if the CPU should deschedule itself. 295 */ 296 void tick(); 297 298 /** Initialize the CPU */ 299 void init(); 300 301 /** Returns the Number of Active Threads in the CPU */ 302 int numActiveThreads() 303 { return activeThreads.size(); } 304 305 /** Add Thread to Active Threads List */ 306 void activateThread(ThreadID tid); 307 308 /** Remove Thread from Active Threads List */ 309 void deactivateThread(ThreadID tid); 310 311 /** Setup CPU to insert a thread's context */ 312 void insertThread(ThreadID tid); 313 314 /** Remove all of a thread's context from CPU */ 315 void removeThread(ThreadID tid); 316 317 /** Count the Total Instructions Committed in the CPU. */ 318 virtual Counter totalInstructions() const; 319 320 /** Add Thread to Active Threads List. */ 321 void activateContext(ThreadID tid, int delay); 322 323 /** Remove Thread from Active Threads List */ 324 void suspendContext(ThreadID tid); 325 326 /** Remove Thread from Active Threads List && 327 * Possibly Remove Thread Context from CPU. 328 */ 329 bool deallocateContext(ThreadID tid, bool remove, int delay = 1); 330 331 /** Remove Thread from Active Threads List && 332 * Remove Thread Context from CPU. 333 */ 334 void haltContext(ThreadID tid); 335 336 /** Activate a Thread When CPU Resources are Available. */ 337 void activateWhenReady(ThreadID tid); 338 339 /** Add or Remove a Thread Context in the CPU. */ 340 void doContextSwitch(); 341 342 /** Update The Order In Which We Process Threads. */ 343 void updateThreadPriority(); 344 345 /** Serialize state. */ 346 virtual void serialize(std::ostream &os); 347 348 /** Unserialize from a checkpoint. */ 349 virtual void unserialize(Checkpoint *cp, const std::string §ion); 350 351 public: 352 /** Executes a syscall. 353 * @todo: Determine if this needs to be virtual. 354 */ 355 void syscall(int64_t callnum, ThreadID tid); 356 357 /** Starts draining the CPU's pipeline of all instructions in 358 * order to stop all memory accesses. */ 359 virtual unsigned int drain(Event *drain_event); 360 361 /** Resumes execution after a drain. */ 362 virtual void resume(); 363 364 /** Signals to this CPU that a stage has completed switching out. */ 365 void signalDrained(); 366 367 /** Switches out this CPU. */ 368 virtual void switchOut(); 369 370 /** Takes over from another CPU. */ 371 virtual void takeOverFrom(BaseCPU *oldCPU); 372 373 /** Get the current instruction sequence number, and increment it. */ 374 InstSeqNum getAndIncrementInstSeq() 375 { return globalSeqNum++; } 376 377 /** Traps to handle given fault. */ 378 void trap(Fault fault, ThreadID tid, StaticInstPtr inst); 379 380 /** HW return from error interrupt. */ 381 Fault hwrei(ThreadID tid); 382 383 bool simPalCheck(int palFunc, ThreadID tid); 384 385 /** Returns the Fault for any valid interrupt. */ 386 Fault getInterrupts(); 387 388 /** Processes any an interrupt fault. */ 389 void processInterrupts(Fault interrupt); 390 391 /** Halts the CPU. */ 392 void halt() { panic("Halt not implemented!\n"); } 393 394 /** Update the Virt and Phys ports of all ThreadContexts to 395 * reflect change in memory connections. */ 396 void updateMemPorts(); 397 398 /** Check if this address is a valid instruction address. */ 399 bool validInstAddr(Addr addr) { return true; } 400 401 /** Check if this address is a valid data address. */ 402 bool validDataAddr(Addr addr) { return true; } 403 404 /** Register accessors. Index refers to the physical register index. */ 405 406 /** Reads a miscellaneous register. */ 407 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid); 408 409 /** Reads a misc. register, including any side effects the read 410 * might have as defined by the architecture. 411 */ 412 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid); 413 414 /** Sets a miscellaneous register. */ 415 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, 416 ThreadID tid); 417 418 /** Sets a misc. register, including any side effects the write 419 * might have as defined by the architecture. 420 */ 421 void setMiscReg(int misc_reg, const TheISA::MiscReg &val, 422 ThreadID tid); 423 424 uint64_t readIntReg(int reg_idx); 425 426 TheISA::FloatReg readFloatReg(int reg_idx); 427 428 TheISA::FloatRegBits readFloatRegBits(int reg_idx); 429 430 void setIntReg(int reg_idx, uint64_t val); 431 432 void setFloatReg(int reg_idx, TheISA::FloatReg val); 433 434 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 435 436 uint64_t readArchIntReg(int reg_idx, ThreadID tid); 437 438 float readArchFloatReg(int reg_idx, ThreadID tid); 439 440 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); 441 442 /** Architectural register accessors. Looks up in the commit 443 * rename table to obtain the true physical index of the 444 * architected register first, then accesses that physical 445 * register. 446 */ 447 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); 448 449 void setArchFloatReg(int reg_idx, float val, ThreadID tid); 450 451 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); 452 453 /** Sets the commit PC state of a specific thread. */ 454 void pcState(const TheISA::PCState &newPCState, ThreadID tid); 455 456 /** Reads the commit PC state of a specific thread. */ 457 TheISA::PCState pcState(ThreadID tid); 458 459 /** Reads the commit PC of a specific thread. */ 460 Addr instAddr(ThreadID tid); 461 462 /** Reads the commit micro PC of a specific thread. */ 463 MicroPC microPC(ThreadID tid); 464 465 /** Reads the next PC of a specific thread. */ 466 Addr nextInstAddr(ThreadID tid); 467 468 /** Initiates a squash of all in-flight instructions for a given 469 * thread. The source of the squash is an external update of 470 * state through the TC. 471 */ 472 void squashFromTC(ThreadID tid); 473 474 /** Function to add instruction onto the head of the list of the 475 * instructions. Used when new instructions are fetched. 476 */ 477 ListIt addInst(DynInstPtr &inst); 478 479 /** Function to tell the CPU that an instruction has completed. */ 480 void instDone(ThreadID tid); 481 482 /** Remove an instruction from the front end of the list. There's 483 * no restriction on location of the instruction. 484 */ 485 void removeFrontInst(DynInstPtr &inst); 486 487 /** Remove all instructions that are not currently in the ROB. 488 * There's also an option to not squash delay slot instructions.*/ 489 void removeInstsNotInROB(ThreadID tid); 490 491 /** Remove all instructions younger than the given sequence number. */ 492 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid); 493 494 /** Removes the instruction pointed to by the iterator. */ 495 inline void squashInstIt(const ListIt &instIt, ThreadID tid); 496 497 /** Cleans up all instructions on the remove list. */ 498 void cleanUpRemovedInsts(); 499 500 /** Debug function to print all instructions on the list. */ 501 void dumpInsts(); 502 503 public: 504#ifndef NDEBUG 505 /** Count of total number of dynamic instructions in flight. */ 506 int instcount; 507#endif 508 509 /** List of all the instructions in flight. */ 510 std::list<DynInstPtr> instList; 511 512 /** List of all the instructions that will be removed at the end of this 513 * cycle. 514 */ 515 std::queue<ListIt> removeList; 516 517#ifdef DEBUG 518 /** Debug structure to keep track of the sequence numbers still in 519 * flight. 520 */ 521 std::set<InstSeqNum> snList; 522#endif 523 524 /** Records if instructions need to be removed this cycle due to 525 * being retired or squashed. 526 */ 527 bool removeInstsThisCycle; 528 529 protected: 530 /** The fetch stage. */ 531 typename CPUPolicy::Fetch fetch; 532 533 /** The decode stage. */ 534 typename CPUPolicy::Decode decode; 535 536 /** The dispatch stage. */ 537 typename CPUPolicy::Rename rename; 538 539 /** The issue/execute/writeback stages. */ 540 typename CPUPolicy::IEW iew; 541 542 /** The commit stage. */ 543 typename CPUPolicy::Commit commit; 544 545 /** The register file. */ 546 typename CPUPolicy::RegFile regFile; 547 548 /** The free list. */ 549 typename CPUPolicy::FreeList freeList; 550 551 /** The rename map. */ 552 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 553 554 /** The commit rename map. */ 555 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 556 557 /** The re-order buffer. */ 558 typename CPUPolicy::ROB rob; 559 560 /** Active Threads List */ 561 std::list<ThreadID> activeThreads; 562 563 /** Integer Register Scoreboard */ 564 Scoreboard scoreboard; 565 566 TheISA::ISA isa[Impl::MaxThreads]; 567 568 public: 569 /** Enum to give each stage a specific index, so when calling 570 * activateStage() or deactivateStage(), they can specify which stage 571 * is being activated/deactivated. 572 */ 573 enum StageIdx { 574 FetchIdx, 575 DecodeIdx, 576 RenameIdx, 577 IEWIdx, 578 CommitIdx, 579 NumStages }; 580 581 /** Typedefs from the Impl to get the structs that each of the 582 * time buffers should use. 583 */ 584 typedef typename CPUPolicy::TimeStruct TimeStruct; 585 586 typedef typename CPUPolicy::FetchStruct FetchStruct; 587 588 typedef typename CPUPolicy::DecodeStruct DecodeStruct; 589 590 typedef typename CPUPolicy::RenameStruct RenameStruct; 591 592 typedef typename CPUPolicy::IEWStruct IEWStruct; 593 594 /** The main time buffer to do backwards communication. */ 595 TimeBuffer<TimeStruct> timeBuffer; 596 597 /** The fetch stage's instruction queue. */ 598 TimeBuffer<FetchStruct> fetchQueue; 599 600 /** The decode stage's instruction queue. */ 601 TimeBuffer<DecodeStruct> decodeQueue; 602 603 /** The rename stage's instruction queue. */ 604 TimeBuffer<RenameStruct> renameQueue; 605 606 /** The IEW stage's instruction queue. */ 607 TimeBuffer<IEWStruct> iewQueue; 608 609 private: 610 /** The activity recorder; used to tell if the CPU has any 611 * activity remaining or if it can go to idle and deschedule 612 * itself. 613 */ 614 ActivityRecorder activityRec; 615 616 public: 617 /** Records that there was time buffer activity this cycle. */ 618 void activityThisCycle() { activityRec.activity(); } 619 620 /** Changes a stage's status to active within the activity recorder. */ 621 void activateStage(const StageIdx idx) 622 { activityRec.activateStage(idx); } 623 624 /** Changes a stage's status to inactive within the activity recorder. */ 625 void deactivateStage(const StageIdx idx) 626 { activityRec.deactivateStage(idx); } 627 628 /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 629 void wakeCPU(); 630 631 virtual void wakeup(); 632 633 /** Gets a free thread id. Use if thread ids change across system. */ 634 ThreadID getFreeTid(); 635 636 public: 637 /** Returns a pointer to a thread context. */ 638 ThreadContext * 639 tcBase(ThreadID tid) 640 { 641 return thread[tid]->getTC(); 642 } 643 644 /** The global sequence number counter. */ 645 InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 646 647#if USE_CHECKER 648 /** Pointer to the checker, which can dynamically verify 649 * instruction results at run time. This can be set to NULL if it 650 * is not being used. 651 */ 652 Checker<DynInstPtr> *checker; 653#endif 654 655 /** Pointer to the system. */ 656 System *system; 657 658 /** Event to call process() on once draining has completed. */ 659 Event *drainEvent; 660 661 /** Counter of how many stages have completed draining. */ 662 int drainCount; 663 664 /** Pointers to all of the threads in the CPU. */ 665 std::vector<Thread *> thread; 666 667 /** Whether or not the CPU should defer its registration. */ 668 bool deferRegistration; 669 670 /** Is there a context switch pending? */ 671 bool contextSwitch; 672 673 /** Threads Scheduled to Enter CPU */ 674 std::list<int> cpuWaitList; 675 676 /** The cycle that the CPU was last running, used for statistics. */ 677 Tick lastRunningCycle; 678 679 /** The cycle that the CPU was last activated by a new thread*/ 680 Tick lastActivatedCycle; 681 682 /** Mapping for system thread id to cpu id */ 683 std::map<ThreadID, unsigned> threadMap; 684 685 /** Available thread ids in the cpu*/ 686 std::vector<ThreadID> tids; 687 688 /** CPU read function, forwards read to LSQ. */ 689 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 690 uint8_t *data, int load_idx) 691 { 692 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, 693 data, load_idx); 694 } 695 696 /** CPU write function, forwards write to LSQ. */ 697 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 698 uint8_t *data, int store_idx) 699 { 700 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh, 701 data, store_idx); 702 } 703 704 /** Get the dcache port (used to find block size for translations). */ 705 Port *getDcachePort() { return this->iew.ldstQueue.getDcachePort(); } 706 707 Addr lockAddr; 708 709 /** Temporary fix for the lock flag, works in the UP case. */ 710 bool lockFlag; 711 712 /** Stat for total number of times the CPU is descheduled. */ 713 Stats::Scalar timesIdled; 714 /** Stat for total number of cycles the CPU spends descheduled. */ 715 Stats::Scalar idleCycles;
| 1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * Copyright (c) 2011 Regents of the University of California 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Kevin Lim 30 * Korey Sewell 31 * Rick Strong 32 */ 33 34#ifndef __CPU_O3_CPU_HH__ 35#define __CPU_O3_CPU_HH__ 36 37#include <iostream> 38#include <list> 39#include <queue> 40#include <set> 41#include <vector> 42 43#include "arch/types.hh" 44#include "base/statistics.hh" 45#include "config/the_isa.hh" 46#include "config/use_checker.hh" 47#include "cpu/o3/comm.hh" 48#include "cpu/o3/cpu_policy.hh" 49#include "cpu/o3/scoreboard.hh" 50#include "cpu/o3/thread_state.hh" 51#include "cpu/activity.hh" 52#include "cpu/base.hh" 53#include "cpu/simple_thread.hh" 54#include "cpu/timebuf.hh" 55//#include "cpu/o3/thread_context.hh" 56#include "params/DerivO3CPU.hh" 57#include "sim/process.hh" 58 59template <class> 60class Checker; 61class ThreadContext; 62template <class> 63class O3ThreadContext; 64 65class Checkpoint; 66class MemObject; 67class Process; 68 69class BaseCPUParams; 70 71class BaseO3CPU : public BaseCPU 72{ 73 //Stuff that's pretty ISA independent will go here. 74 public: 75 BaseO3CPU(BaseCPUParams *params); 76 77 void regStats(); 78}; 79 80/** 81 * FullO3CPU class, has each of the stages (fetch through commit) 82 * within it, as well as all of the time buffers between stages. The 83 * tick() function for the CPU is defined here. 84 */ 85template <class Impl> 86class FullO3CPU : public BaseO3CPU 87{ 88 public: 89 // Typedefs from the Impl here. 90 typedef typename Impl::CPUPol CPUPolicy; 91 typedef typename Impl::DynInstPtr DynInstPtr; 92 typedef typename Impl::O3CPU O3CPU; 93 94 typedef O3ThreadState<Impl> ImplState; 95 typedef O3ThreadState<Impl> Thread; 96 97 typedef typename std::list<DynInstPtr>::iterator ListIt; 98 99 friend class O3ThreadContext<Impl>; 100 101 public: 102 enum Status { 103 Running, 104 Idle, 105 Halted, 106 Blocked, 107 SwitchedOut 108 }; 109 110 TheISA::TLB * itb; 111 TheISA::TLB * dtb; 112 113 /** Overall CPU status. */ 114 Status _status; 115 116 /** Per-thread status in CPU, used for SMT. */ 117 Status _threadStatus[Impl::MaxThreads]; 118 119 private: 120 class TickEvent : public Event 121 { 122 private: 123 /** Pointer to the CPU. */ 124 FullO3CPU<Impl> *cpu; 125 126 public: 127 /** Constructs a tick event. */ 128 TickEvent(FullO3CPU<Impl> *c); 129 130 /** Processes a tick event, calling tick() on the CPU. */ 131 void process(); 132 /** Returns the description of the tick event. */ 133 const char *description() const; 134 }; 135 136 /** The tick event used for scheduling CPU ticks. */ 137 TickEvent tickEvent; 138 139 /** Schedule tick event, regardless of its current state. */ 140 void scheduleTickEvent(int delay) 141 { 142 if (tickEvent.squashed()) 143 reschedule(tickEvent, nextCycle(curTick() + ticks(delay))); 144 else if (!tickEvent.scheduled()) 145 schedule(tickEvent, nextCycle(curTick() + ticks(delay))); 146 } 147 148 /** Unschedule tick event, regardless of its current state. */ 149 void unscheduleTickEvent() 150 { 151 if (tickEvent.scheduled()) 152 tickEvent.squash(); 153 } 154 155 class ActivateThreadEvent : public Event 156 { 157 private: 158 /** Number of Thread to Activate */ 159 ThreadID tid; 160 161 /** Pointer to the CPU. */ 162 FullO3CPU<Impl> *cpu; 163 164 public: 165 /** Constructs the event. */ 166 ActivateThreadEvent(); 167 168 /** Initialize Event */ 169 void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 170 171 /** Processes the event, calling activateThread() on the CPU. */ 172 void process(); 173 174 /** Returns the description of the event. */ 175 const char *description() const; 176 }; 177 178 /** Schedule thread to activate , regardless of its current state. */ 179 void 180 scheduleActivateThreadEvent(ThreadID tid, int delay) 181 { 182 // Schedule thread to activate, regardless of its current state. 183 if (activateThreadEvent[tid].squashed()) 184 reschedule(activateThreadEvent[tid], 185 nextCycle(curTick() + ticks(delay))); 186 else if (!activateThreadEvent[tid].scheduled()) { 187 Tick when = nextCycle(curTick() + ticks(delay)); 188 189 // Check if the deallocateEvent is also scheduled, and make 190 // sure they do not happen at same time causing a sleep that 191 // is never woken from. 192 if (deallocateContextEvent[tid].scheduled() && 193 deallocateContextEvent[tid].when() == when) { 194 when++; 195 } 196 197 schedule(activateThreadEvent[tid], when); 198 } 199 } 200 201 /** Unschedule actiavte thread event, regardless of its current state. */ 202 void 203 unscheduleActivateThreadEvent(ThreadID tid) 204 { 205 if (activateThreadEvent[tid].scheduled()) 206 activateThreadEvent[tid].squash(); 207 } 208 209 /** The tick event used for scheduling CPU ticks. */ 210 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 211 212 class DeallocateContextEvent : public Event 213 { 214 private: 215 /** Number of Thread to deactivate */ 216 ThreadID tid; 217 218 /** Should the thread be removed from the CPU? */ 219 bool remove; 220 221 /** Pointer to the CPU. */ 222 FullO3CPU<Impl> *cpu; 223 224 public: 225 /** Constructs the event. */ 226 DeallocateContextEvent(); 227 228 /** Initialize Event */ 229 void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 230 231 /** Processes the event, calling activateThread() on the CPU. */ 232 void process(); 233 234 /** Sets whether the thread should also be removed from the CPU. */ 235 void setRemove(bool _remove) { remove = _remove; } 236 237 /** Returns the description of the event. */ 238 const char *description() const; 239 }; 240 241 /** Schedule cpu to deallocate thread context.*/ 242 void 243 scheduleDeallocateContextEvent(ThreadID tid, bool remove, int delay) 244 { 245 // Schedule thread to activate, regardless of its current state. 246 if (deallocateContextEvent[tid].squashed()) 247 reschedule(deallocateContextEvent[tid], 248 nextCycle(curTick() + ticks(delay))); 249 else if (!deallocateContextEvent[tid].scheduled()) 250 schedule(deallocateContextEvent[tid], 251 nextCycle(curTick() + ticks(delay))); 252 } 253 254 /** Unschedule thread deallocation in CPU */ 255 void 256 unscheduleDeallocateContextEvent(ThreadID tid) 257 { 258 if (deallocateContextEvent[tid].scheduled()) 259 deallocateContextEvent[tid].squash(); 260 } 261 262 /** The tick event used for scheduling CPU ticks. */ 263 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads]; 264 265 public: 266 /** Constructs a CPU with the given parameters. */ 267 FullO3CPU(DerivO3CPUParams *params); 268 /** Destructor. */ 269 ~FullO3CPU(); 270 271 /** Registers statistics. */ 272 void regStats(); 273 274 void demapPage(Addr vaddr, uint64_t asn) 275 { 276 this->itb->demapPage(vaddr, asn); 277 this->dtb->demapPage(vaddr, asn); 278 } 279 280 void demapInstPage(Addr vaddr, uint64_t asn) 281 { 282 this->itb->demapPage(vaddr, asn); 283 } 284 285 void demapDataPage(Addr vaddr, uint64_t asn) 286 { 287 this->dtb->demapPage(vaddr, asn); 288 } 289 290 /** Returns a specific port. */ 291 Port *getPort(const std::string &if_name, int idx); 292 293 /** Ticks CPU, calling tick() on each stage, and checking the overall 294 * activity to see if the CPU should deschedule itself. 295 */ 296 void tick(); 297 298 /** Initialize the CPU */ 299 void init(); 300 301 /** Returns the Number of Active Threads in the CPU */ 302 int numActiveThreads() 303 { return activeThreads.size(); } 304 305 /** Add Thread to Active Threads List */ 306 void activateThread(ThreadID tid); 307 308 /** Remove Thread from Active Threads List */ 309 void deactivateThread(ThreadID tid); 310 311 /** Setup CPU to insert a thread's context */ 312 void insertThread(ThreadID tid); 313 314 /** Remove all of a thread's context from CPU */ 315 void removeThread(ThreadID tid); 316 317 /** Count the Total Instructions Committed in the CPU. */ 318 virtual Counter totalInstructions() const; 319 320 /** Add Thread to Active Threads List. */ 321 void activateContext(ThreadID tid, int delay); 322 323 /** Remove Thread from Active Threads List */ 324 void suspendContext(ThreadID tid); 325 326 /** Remove Thread from Active Threads List && 327 * Possibly Remove Thread Context from CPU. 328 */ 329 bool deallocateContext(ThreadID tid, bool remove, int delay = 1); 330 331 /** Remove Thread from Active Threads List && 332 * Remove Thread Context from CPU. 333 */ 334 void haltContext(ThreadID tid); 335 336 /** Activate a Thread When CPU Resources are Available. */ 337 void activateWhenReady(ThreadID tid); 338 339 /** Add or Remove a Thread Context in the CPU. */ 340 void doContextSwitch(); 341 342 /** Update The Order In Which We Process Threads. */ 343 void updateThreadPriority(); 344 345 /** Serialize state. */ 346 virtual void serialize(std::ostream &os); 347 348 /** Unserialize from a checkpoint. */ 349 virtual void unserialize(Checkpoint *cp, const std::string §ion); 350 351 public: 352 /** Executes a syscall. 353 * @todo: Determine if this needs to be virtual. 354 */ 355 void syscall(int64_t callnum, ThreadID tid); 356 357 /** Starts draining the CPU's pipeline of all instructions in 358 * order to stop all memory accesses. */ 359 virtual unsigned int drain(Event *drain_event); 360 361 /** Resumes execution after a drain. */ 362 virtual void resume(); 363 364 /** Signals to this CPU that a stage has completed switching out. */ 365 void signalDrained(); 366 367 /** Switches out this CPU. */ 368 virtual void switchOut(); 369 370 /** Takes over from another CPU. */ 371 virtual void takeOverFrom(BaseCPU *oldCPU); 372 373 /** Get the current instruction sequence number, and increment it. */ 374 InstSeqNum getAndIncrementInstSeq() 375 { return globalSeqNum++; } 376 377 /** Traps to handle given fault. */ 378 void trap(Fault fault, ThreadID tid, StaticInstPtr inst); 379 380 /** HW return from error interrupt. */ 381 Fault hwrei(ThreadID tid); 382 383 bool simPalCheck(int palFunc, ThreadID tid); 384 385 /** Returns the Fault for any valid interrupt. */ 386 Fault getInterrupts(); 387 388 /** Processes any an interrupt fault. */ 389 void processInterrupts(Fault interrupt); 390 391 /** Halts the CPU. */ 392 void halt() { panic("Halt not implemented!\n"); } 393 394 /** Update the Virt and Phys ports of all ThreadContexts to 395 * reflect change in memory connections. */ 396 void updateMemPorts(); 397 398 /** Check if this address is a valid instruction address. */ 399 bool validInstAddr(Addr addr) { return true; } 400 401 /** Check if this address is a valid data address. */ 402 bool validDataAddr(Addr addr) { return true; } 403 404 /** Register accessors. Index refers to the physical register index. */ 405 406 /** Reads a miscellaneous register. */ 407 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid); 408 409 /** Reads a misc. register, including any side effects the read 410 * might have as defined by the architecture. 411 */ 412 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid); 413 414 /** Sets a miscellaneous register. */ 415 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, 416 ThreadID tid); 417 418 /** Sets a misc. register, including any side effects the write 419 * might have as defined by the architecture. 420 */ 421 void setMiscReg(int misc_reg, const TheISA::MiscReg &val, 422 ThreadID tid); 423 424 uint64_t readIntReg(int reg_idx); 425 426 TheISA::FloatReg readFloatReg(int reg_idx); 427 428 TheISA::FloatRegBits readFloatRegBits(int reg_idx); 429 430 void setIntReg(int reg_idx, uint64_t val); 431 432 void setFloatReg(int reg_idx, TheISA::FloatReg val); 433 434 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 435 436 uint64_t readArchIntReg(int reg_idx, ThreadID tid); 437 438 float readArchFloatReg(int reg_idx, ThreadID tid); 439 440 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); 441 442 /** Architectural register accessors. Looks up in the commit 443 * rename table to obtain the true physical index of the 444 * architected register first, then accesses that physical 445 * register. 446 */ 447 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); 448 449 void setArchFloatReg(int reg_idx, float val, ThreadID tid); 450 451 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); 452 453 /** Sets the commit PC state of a specific thread. */ 454 void pcState(const TheISA::PCState &newPCState, ThreadID tid); 455 456 /** Reads the commit PC state of a specific thread. */ 457 TheISA::PCState pcState(ThreadID tid); 458 459 /** Reads the commit PC of a specific thread. */ 460 Addr instAddr(ThreadID tid); 461 462 /** Reads the commit micro PC of a specific thread. */ 463 MicroPC microPC(ThreadID tid); 464 465 /** Reads the next PC of a specific thread. */ 466 Addr nextInstAddr(ThreadID tid); 467 468 /** Initiates a squash of all in-flight instructions for a given 469 * thread. The source of the squash is an external update of 470 * state through the TC. 471 */ 472 void squashFromTC(ThreadID tid); 473 474 /** Function to add instruction onto the head of the list of the 475 * instructions. Used when new instructions are fetched. 476 */ 477 ListIt addInst(DynInstPtr &inst); 478 479 /** Function to tell the CPU that an instruction has completed. */ 480 void instDone(ThreadID tid); 481 482 /** Remove an instruction from the front end of the list. There's 483 * no restriction on location of the instruction. 484 */ 485 void removeFrontInst(DynInstPtr &inst); 486 487 /** Remove all instructions that are not currently in the ROB. 488 * There's also an option to not squash delay slot instructions.*/ 489 void removeInstsNotInROB(ThreadID tid); 490 491 /** Remove all instructions younger than the given sequence number. */ 492 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid); 493 494 /** Removes the instruction pointed to by the iterator. */ 495 inline void squashInstIt(const ListIt &instIt, ThreadID tid); 496 497 /** Cleans up all instructions on the remove list. */ 498 void cleanUpRemovedInsts(); 499 500 /** Debug function to print all instructions on the list. */ 501 void dumpInsts(); 502 503 public: 504#ifndef NDEBUG 505 /** Count of total number of dynamic instructions in flight. */ 506 int instcount; 507#endif 508 509 /** List of all the instructions in flight. */ 510 std::list<DynInstPtr> instList; 511 512 /** List of all the instructions that will be removed at the end of this 513 * cycle. 514 */ 515 std::queue<ListIt> removeList; 516 517#ifdef DEBUG 518 /** Debug structure to keep track of the sequence numbers still in 519 * flight. 520 */ 521 std::set<InstSeqNum> snList; 522#endif 523 524 /** Records if instructions need to be removed this cycle due to 525 * being retired or squashed. 526 */ 527 bool removeInstsThisCycle; 528 529 protected: 530 /** The fetch stage. */ 531 typename CPUPolicy::Fetch fetch; 532 533 /** The decode stage. */ 534 typename CPUPolicy::Decode decode; 535 536 /** The dispatch stage. */ 537 typename CPUPolicy::Rename rename; 538 539 /** The issue/execute/writeback stages. */ 540 typename CPUPolicy::IEW iew; 541 542 /** The commit stage. */ 543 typename CPUPolicy::Commit commit; 544 545 /** The register file. */ 546 typename CPUPolicy::RegFile regFile; 547 548 /** The free list. */ 549 typename CPUPolicy::FreeList freeList; 550 551 /** The rename map. */ 552 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 553 554 /** The commit rename map. */ 555 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 556 557 /** The re-order buffer. */ 558 typename CPUPolicy::ROB rob; 559 560 /** Active Threads List */ 561 std::list<ThreadID> activeThreads; 562 563 /** Integer Register Scoreboard */ 564 Scoreboard scoreboard; 565 566 TheISA::ISA isa[Impl::MaxThreads]; 567 568 public: 569 /** Enum to give each stage a specific index, so when calling 570 * activateStage() or deactivateStage(), they can specify which stage 571 * is being activated/deactivated. 572 */ 573 enum StageIdx { 574 FetchIdx, 575 DecodeIdx, 576 RenameIdx, 577 IEWIdx, 578 CommitIdx, 579 NumStages }; 580 581 /** Typedefs from the Impl to get the structs that each of the 582 * time buffers should use. 583 */ 584 typedef typename CPUPolicy::TimeStruct TimeStruct; 585 586 typedef typename CPUPolicy::FetchStruct FetchStruct; 587 588 typedef typename CPUPolicy::DecodeStruct DecodeStruct; 589 590 typedef typename CPUPolicy::RenameStruct RenameStruct; 591 592 typedef typename CPUPolicy::IEWStruct IEWStruct; 593 594 /** The main time buffer to do backwards communication. */ 595 TimeBuffer<TimeStruct> timeBuffer; 596 597 /** The fetch stage's instruction queue. */ 598 TimeBuffer<FetchStruct> fetchQueue; 599 600 /** The decode stage's instruction queue. */ 601 TimeBuffer<DecodeStruct> decodeQueue; 602 603 /** The rename stage's instruction queue. */ 604 TimeBuffer<RenameStruct> renameQueue; 605 606 /** The IEW stage's instruction queue. */ 607 TimeBuffer<IEWStruct> iewQueue; 608 609 private: 610 /** The activity recorder; used to tell if the CPU has any 611 * activity remaining or if it can go to idle and deschedule 612 * itself. 613 */ 614 ActivityRecorder activityRec; 615 616 public: 617 /** Records that there was time buffer activity this cycle. */ 618 void activityThisCycle() { activityRec.activity(); } 619 620 /** Changes a stage's status to active within the activity recorder. */ 621 void activateStage(const StageIdx idx) 622 { activityRec.activateStage(idx); } 623 624 /** Changes a stage's status to inactive within the activity recorder. */ 625 void deactivateStage(const StageIdx idx) 626 { activityRec.deactivateStage(idx); } 627 628 /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 629 void wakeCPU(); 630 631 virtual void wakeup(); 632 633 /** Gets a free thread id. Use if thread ids change across system. */ 634 ThreadID getFreeTid(); 635 636 public: 637 /** Returns a pointer to a thread context. */ 638 ThreadContext * 639 tcBase(ThreadID tid) 640 { 641 return thread[tid]->getTC(); 642 } 643 644 /** The global sequence number counter. */ 645 InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 646 647#if USE_CHECKER 648 /** Pointer to the checker, which can dynamically verify 649 * instruction results at run time. This can be set to NULL if it 650 * is not being used. 651 */ 652 Checker<DynInstPtr> *checker; 653#endif 654 655 /** Pointer to the system. */ 656 System *system; 657 658 /** Event to call process() on once draining has completed. */ 659 Event *drainEvent; 660 661 /** Counter of how many stages have completed draining. */ 662 int drainCount; 663 664 /** Pointers to all of the threads in the CPU. */ 665 std::vector<Thread *> thread; 666 667 /** Whether or not the CPU should defer its registration. */ 668 bool deferRegistration; 669 670 /** Is there a context switch pending? */ 671 bool contextSwitch; 672 673 /** Threads Scheduled to Enter CPU */ 674 std::list<int> cpuWaitList; 675 676 /** The cycle that the CPU was last running, used for statistics. */ 677 Tick lastRunningCycle; 678 679 /** The cycle that the CPU was last activated by a new thread*/ 680 Tick lastActivatedCycle; 681 682 /** Mapping for system thread id to cpu id */ 683 std::map<ThreadID, unsigned> threadMap; 684 685 /** Available thread ids in the cpu*/ 686 std::vector<ThreadID> tids; 687 688 /** CPU read function, forwards read to LSQ. */ 689 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 690 uint8_t *data, int load_idx) 691 { 692 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, 693 data, load_idx); 694 } 695 696 /** CPU write function, forwards write to LSQ. */ 697 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 698 uint8_t *data, int store_idx) 699 { 700 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh, 701 data, store_idx); 702 } 703 704 /** Get the dcache port (used to find block size for translations). */ 705 Port *getDcachePort() { return this->iew.ldstQueue.getDcachePort(); } 706 707 Addr lockAddr; 708 709 /** Temporary fix for the lock flag, works in the UP case. */ 710 bool lockFlag; 711 712 /** Stat for total number of times the CPU is descheduled. */ 713 Stats::Scalar timesIdled; 714 /** Stat for total number of cycles the CPU spends descheduled. */ 715 Stats::Scalar idleCycles;
|