1/*
| 1/*
|
| 2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
|
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * Copyright (c) 2011 Regents of the University of California
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Kevin Lim
30 * Korey Sewell
31 * Rick Strong
32 */
33
34#ifndef __CPU_O3_CPU_HH__
35#define __CPU_O3_CPU_HH__
36
37#include <iostream>
38#include <list>
39#include <queue>
40#include <set>
41#include <vector>
42
43#include "arch/types.hh"
44#include "base/statistics.hh"
45#include "config/full_system.hh"
46#include "config/the_isa.hh"
47#include "config/use_checker.hh"
48#include "cpu/o3/comm.hh"
49#include "cpu/o3/cpu_policy.hh"
50#include "cpu/o3/scoreboard.hh"
51#include "cpu/o3/thread_state.hh"
52#include "cpu/activity.hh"
53#include "cpu/base.hh"
54#include "cpu/simple_thread.hh"
55#include "cpu/timebuf.hh"
56//#include "cpu/o3/thread_context.hh"
57#include "params/DerivO3CPU.hh"
58#include "sim/process.hh"
59
60template <class>
61class Checker;
62class ThreadContext;
63template <class>
64class O3ThreadContext;
65
66class Checkpoint;
67class MemObject;
68class Process;
69
70class BaseCPUParams;
71
72class BaseO3CPU : public BaseCPU
73{
74 //Stuff that's pretty ISA independent will go here.
75 public:
76 BaseO3CPU(BaseCPUParams *params);
77
78 void regStats();
79};
80
81/**
82 * FullO3CPU class, has each of the stages (fetch through commit)
83 * within it, as well as all of the time buffers between stages. The
84 * tick() function for the CPU is defined here.
85 */
86template <class Impl>
87class FullO3CPU : public BaseO3CPU
88{
89 public:
90 // Typedefs from the Impl here.
91 typedef typename Impl::CPUPol CPUPolicy;
92 typedef typename Impl::DynInstPtr DynInstPtr;
93 typedef typename Impl::O3CPU O3CPU;
94
95 typedef O3ThreadState<Impl> ImplState;
96 typedef O3ThreadState<Impl> Thread;
97
98 typedef typename std::list<DynInstPtr>::iterator ListIt;
99
100 friend class O3ThreadContext<Impl>;
101
102 public:
103 enum Status {
104 Running,
105 Idle,
106 Halted,
107 Blocked,
108 SwitchedOut
109 };
110
111 TheISA::TLB * itb;
112 TheISA::TLB * dtb;
113
114 /** Overall CPU status. */
115 Status _status;
116
117 /** Per-thread status in CPU, used for SMT. */
118 Status _threadStatus[Impl::MaxThreads];
119
120 private:
| 14 * Copyright (c) 2004-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 * Rick Strong
44 */
45
46#ifndef __CPU_O3_CPU_HH__
47#define __CPU_O3_CPU_HH__
48
49#include <iostream>
50#include <list>
51#include <queue>
52#include <set>
53#include <vector>
54
55#include "arch/types.hh"
56#include "base/statistics.hh"
57#include "config/full_system.hh"
58#include "config/the_isa.hh"
59#include "config/use_checker.hh"
60#include "cpu/o3/comm.hh"
61#include "cpu/o3/cpu_policy.hh"
62#include "cpu/o3/scoreboard.hh"
63#include "cpu/o3/thread_state.hh"
64#include "cpu/activity.hh"
65#include "cpu/base.hh"
66#include "cpu/simple_thread.hh"
67#include "cpu/timebuf.hh"
68//#include "cpu/o3/thread_context.hh"
69#include "params/DerivO3CPU.hh"
70#include "sim/process.hh"
71
72template <class>
73class Checker;
74class ThreadContext;
75template <class>
76class O3ThreadContext;
77
78class Checkpoint;
79class MemObject;
80class Process;
81
82class BaseCPUParams;
83
84class BaseO3CPU : public BaseCPU
85{
86 //Stuff that's pretty ISA independent will go here.
87 public:
88 BaseO3CPU(BaseCPUParams *params);
89
90 void regStats();
91};
92
93/**
94 * FullO3CPU class, has each of the stages (fetch through commit)
95 * within it, as well as all of the time buffers between stages. The
96 * tick() function for the CPU is defined here.
97 */
98template <class Impl>
99class FullO3CPU : public BaseO3CPU
100{
101 public:
102 // Typedefs from the Impl here.
103 typedef typename Impl::CPUPol CPUPolicy;
104 typedef typename Impl::DynInstPtr DynInstPtr;
105 typedef typename Impl::O3CPU O3CPU;
106
107 typedef O3ThreadState<Impl> ImplState;
108 typedef O3ThreadState<Impl> Thread;
109
110 typedef typename std::list<DynInstPtr>::iterator ListIt;
111
112 friend class O3ThreadContext<Impl>;
113
114 public:
115 enum Status {
116 Running,
117 Idle,
118 Halted,
119 Blocked,
120 SwitchedOut
121 };
122
123 TheISA::TLB * itb;
124 TheISA::TLB * dtb;
125
126 /** Overall CPU status. */
127 Status _status;
128
129 /** Per-thread status in CPU, used for SMT. */
130 Status _threadStatus[Impl::MaxThreads];
131
132 private:
|
| 133
134 /**
135 * IcachePort class for instruction fetch.
136 */
137 class IcachePort : public CpuPort
138 {
139 protected:
140 /** Pointer to fetch. */
141 DefaultFetch<Impl> *fetch;
142
143 public:
144 /** Default constructor. */
145 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
146 : CpuPort(_fetch->name() + "-iport", _cpu), fetch(_fetch)
147 { }
148
149 protected:
150
151 /** Timing version of receive. Handles setting fetch to the
152 * proper status to start fetching. */
153 virtual bool recvTiming(PacketPtr pkt);
154
155 /** Handles doing a retry of a failed fetch. */
156 virtual void recvRetry();
157 };
158
159 /**
160 * DcachePort class for the load/store queue.
161 */
162 class DcachePort : public CpuPort
163 {
164 protected:
165
166 /** Pointer to LSQ. */
167 LSQ<Impl> *lsq;
168
169 public:
170 /** Default constructor. */
171 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
172 : CpuPort(_lsq->name() + "-dport", _cpu), lsq(_lsq)
173 { }
174
175 protected:
176
177 /** Timing version of receive. Handles writing back and
178 * completing the load or store that has returned from
179 * memory. */
180 virtual bool recvTiming(PacketPtr pkt);
181
182 /** Handles doing a retry of the previous send. */
183 virtual void recvRetry();
184
185 /**
186 * As this CPU requires snooping to maintain the load store queue
187 * change the behaviour from the base CPU port.
188 *
189 * @param resp list of ranges this port responds to
190 * @param snoop indicating if the port snoops or not
191 */
192 virtual void getDeviceAddressRanges(AddrRangeList& resp,
193 bool& snoop)
194 { resp.clear(); snoop = true; }
195 };
196
|
121 class TickEvent : public Event
122 {
123 private:
124 /** Pointer to the CPU. */
125 FullO3CPU<Impl> *cpu;
126
127 public:
128 /** Constructs a tick event. */
129 TickEvent(FullO3CPU<Impl> *c);
130
131 /** Processes a tick event, calling tick() on the CPU. */
132 void process();
133 /** Returns the description of the tick event. */
134 const char *description() const;
135 };
136
137 /** The tick event used for scheduling CPU ticks. */
138 TickEvent tickEvent;
139
140 /** Schedule tick event, regardless of its current state. */
141 void scheduleTickEvent(int delay)
142 {
143 if (tickEvent.squashed())
144 reschedule(tickEvent, nextCycle(curTick() + ticks(delay)));
145 else if (!tickEvent.scheduled())
146 schedule(tickEvent, nextCycle(curTick() + ticks(delay)));
147 }
148
149 /** Unschedule tick event, regardless of its current state. */
150 void unscheduleTickEvent()
151 {
152 if (tickEvent.scheduled())
153 tickEvent.squash();
154 }
155
156 class ActivateThreadEvent : public Event
157 {
158 private:
159 /** Number of Thread to Activate */
160 ThreadID tid;
161
162 /** Pointer to the CPU. */
163 FullO3CPU<Impl> *cpu;
164
165 public:
166 /** Constructs the event. */
167 ActivateThreadEvent();
168
169 /** Initialize Event */
170 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
171
172 /** Processes the event, calling activateThread() on the CPU. */
173 void process();
174
175 /** Returns the description of the event. */
176 const char *description() const;
177 };
178
179 /** Schedule thread to activate , regardless of its current state. */
180 void
181 scheduleActivateThreadEvent(ThreadID tid, int delay)
182 {
183 // Schedule thread to activate, regardless of its current state.
184 if (activateThreadEvent[tid].squashed())
185 reschedule(activateThreadEvent[tid],
186 nextCycle(curTick() + ticks(delay)));
187 else if (!activateThreadEvent[tid].scheduled()) {
188 Tick when = nextCycle(curTick() + ticks(delay));
189
190 // Check if the deallocateEvent is also scheduled, and make
191 // sure they do not happen at same time causing a sleep that
192 // is never woken from.
193 if (deallocateContextEvent[tid].scheduled() &&
194 deallocateContextEvent[tid].when() == when) {
195 when++;
196 }
197
198 schedule(activateThreadEvent[tid], when);
199 }
200 }
201
202 /** Unschedule actiavte thread event, regardless of its current state. */
203 void
204 unscheduleActivateThreadEvent(ThreadID tid)
205 {
206 if (activateThreadEvent[tid].scheduled())
207 activateThreadEvent[tid].squash();
208 }
209
210 /** The tick event used for scheduling CPU ticks. */
211 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
212
213 class DeallocateContextEvent : public Event
214 {
215 private:
216 /** Number of Thread to deactivate */
217 ThreadID tid;
218
219 /** Should the thread be removed from the CPU? */
220 bool remove;
221
222 /** Pointer to the CPU. */
223 FullO3CPU<Impl> *cpu;
224
225 public:
226 /** Constructs the event. */
227 DeallocateContextEvent();
228
229 /** Initialize Event */
230 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
231
232 /** Processes the event, calling activateThread() on the CPU. */
233 void process();
234
235 /** Sets whether the thread should also be removed from the CPU. */
236 void setRemove(bool _remove) { remove = _remove; }
237
238 /** Returns the description of the event. */
239 const char *description() const;
240 };
241
242 /** Schedule cpu to deallocate thread context.*/
243 void
244 scheduleDeallocateContextEvent(ThreadID tid, bool remove, int delay)
245 {
246 // Schedule thread to activate, regardless of its current state.
247 if (deallocateContextEvent[tid].squashed())
248 reschedule(deallocateContextEvent[tid],
249 nextCycle(curTick() + ticks(delay)));
250 else if (!deallocateContextEvent[tid].scheduled())
251 schedule(deallocateContextEvent[tid],
252 nextCycle(curTick() + ticks(delay)));
253 }
254
255 /** Unschedule thread deallocation in CPU */
256 void
257 unscheduleDeallocateContextEvent(ThreadID tid)
258 {
259 if (deallocateContextEvent[tid].scheduled())
260 deallocateContextEvent[tid].squash();
261 }
262
263 /** The tick event used for scheduling CPU ticks. */
264 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
265
266 public:
267 /** Constructs a CPU with the given parameters. */
268 FullO3CPU(DerivO3CPUParams *params);
269 /** Destructor. */
270 ~FullO3CPU();
271
272 /** Registers statistics. */
273 void regStats();
274
275 void demapPage(Addr vaddr, uint64_t asn)
276 {
277 this->itb->demapPage(vaddr, asn);
278 this->dtb->demapPage(vaddr, asn);
279 }
280
281 void demapInstPage(Addr vaddr, uint64_t asn)
282 {
283 this->itb->demapPage(vaddr, asn);
284 }
285
286 void demapDataPage(Addr vaddr, uint64_t asn)
287 {
288 this->dtb->demapPage(vaddr, asn);
289 }
290
291 /** Returns a specific port. */
292 Port *getPort(const std::string &if_name, int idx);
293
294 /** Ticks CPU, calling tick() on each stage, and checking the overall
295 * activity to see if the CPU should deschedule itself.
296 */
297 void tick();
298
299 /** Initialize the CPU */
300 void init();
301
302 /** Returns the Number of Active Threads in the CPU */
303 int numActiveThreads()
304 { return activeThreads.size(); }
305
306 /** Add Thread to Active Threads List */
307 void activateThread(ThreadID tid);
308
309 /** Remove Thread from Active Threads List */
310 void deactivateThread(ThreadID tid);
311
312 /** Setup CPU to insert a thread's context */
313 void insertThread(ThreadID tid);
314
315 /** Remove all of a thread's context from CPU */
316 void removeThread(ThreadID tid);
317
318 /** Count the Total Instructions Committed in the CPU. */
319 virtual Counter totalInstructions() const;
320
321 /** Add Thread to Active Threads List. */
322 void activateContext(ThreadID tid, int delay);
323
324 /** Remove Thread from Active Threads List */
325 void suspendContext(ThreadID tid);
326
327 /** Remove Thread from Active Threads List &&
328 * Possibly Remove Thread Context from CPU.
329 */
330 bool deallocateContext(ThreadID tid, bool remove, int delay = 1);
331
332 /** Remove Thread from Active Threads List &&
333 * Remove Thread Context from CPU.
334 */
335 void haltContext(ThreadID tid);
336
337 /** Activate a Thread When CPU Resources are Available. */
338 void activateWhenReady(ThreadID tid);
339
340 /** Add or Remove a Thread Context in the CPU. */
341 void doContextSwitch();
342
343 /** Update The Order In Which We Process Threads. */
344 void updateThreadPriority();
345
346 /** Serialize state. */
347 virtual void serialize(std::ostream &os);
348
349 /** Unserialize from a checkpoint. */
350 virtual void unserialize(Checkpoint *cp, const std::string §ion);
351
352 public:
353#if !FULL_SYSTEM
354 /** Executes a syscall.
355 * @todo: Determine if this needs to be virtual.
356 */
357 void syscall(int64_t callnum, ThreadID tid);
358#endif
359
360 /** Starts draining the CPU's pipeline of all instructions in
361 * order to stop all memory accesses. */
362 virtual unsigned int drain(Event *drain_event);
363
364 /** Resumes execution after a drain. */
365 virtual void resume();
366
367 /** Signals to this CPU that a stage has completed switching out. */
368 void signalDrained();
369
370 /** Switches out this CPU. */
371 virtual void switchOut();
372
373 /** Takes over from another CPU. */
374 virtual void takeOverFrom(BaseCPU *oldCPU);
375
376 /** Get the current instruction sequence number, and increment it. */
377 InstSeqNum getAndIncrementInstSeq()
378 { return globalSeqNum++; }
379
380 /** Traps to handle given fault. */
381 void trap(Fault fault, ThreadID tid, StaticInstPtr inst);
382
383#if FULL_SYSTEM
384 /** HW return from error interrupt. */
385 Fault hwrei(ThreadID tid);
386
387 bool simPalCheck(int palFunc, ThreadID tid);
388
389 /** Returns the Fault for any valid interrupt. */
390 Fault getInterrupts();
391
392 /** Processes any an interrupt fault. */
393 void processInterrupts(Fault interrupt);
394
395 /** Halts the CPU. */
396 void halt() { panic("Halt not implemented!\n"); }
397
398 /** Check if this address is a valid instruction address. */
399 bool validInstAddr(Addr addr) { return true; }
400
401 /** Check if this address is a valid data address. */
402 bool validDataAddr(Addr addr) { return true; }
403#endif
404
405 /** Register accessors. Index refers to the physical register index. */
406
407 /** Reads a miscellaneous register. */
408 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
409
410 /** Reads a misc. register, including any side effects the read
411 * might have as defined by the architecture.
412 */
413 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
414
415 /** Sets a miscellaneous register. */
416 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
417 ThreadID tid);
418
419 /** Sets a misc. register, including any side effects the write
420 * might have as defined by the architecture.
421 */
422 void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
423 ThreadID tid);
424
425 uint64_t readIntReg(int reg_idx);
426
427 TheISA::FloatReg readFloatReg(int reg_idx);
428
429 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
430
431 void setIntReg(int reg_idx, uint64_t val);
432
433 void setFloatReg(int reg_idx, TheISA::FloatReg val);
434
435 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
436
437 uint64_t readArchIntReg(int reg_idx, ThreadID tid);
438
439 float readArchFloatReg(int reg_idx, ThreadID tid);
440
441 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
442
443 /** Architectural register accessors. Looks up in the commit
444 * rename table to obtain the true physical index of the
445 * architected register first, then accesses that physical
446 * register.
447 */
448 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
449
450 void setArchFloatReg(int reg_idx, float val, ThreadID tid);
451
452 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
453
454 /** Sets the commit PC state of a specific thread. */
455 void pcState(const TheISA::PCState &newPCState, ThreadID tid);
456
457 /** Reads the commit PC state of a specific thread. */
458 TheISA::PCState pcState(ThreadID tid);
459
460 /** Reads the commit PC of a specific thread. */
461 Addr instAddr(ThreadID tid);
462
463 /** Reads the commit micro PC of a specific thread. */
464 MicroPC microPC(ThreadID tid);
465
466 /** Reads the next PC of a specific thread. */
467 Addr nextInstAddr(ThreadID tid);
468
469 /** Initiates a squash of all in-flight instructions for a given
470 * thread. The source of the squash is an external update of
471 * state through the TC.
472 */
473 void squashFromTC(ThreadID tid);
474
475 /** Function to add instruction onto the head of the list of the
476 * instructions. Used when new instructions are fetched.
477 */
478 ListIt addInst(DynInstPtr &inst);
479
480 /** Function to tell the CPU that an instruction has completed. */
481 void instDone(ThreadID tid);
482
483 /** Remove an instruction from the front end of the list. There's
484 * no restriction on location of the instruction.
485 */
486 void removeFrontInst(DynInstPtr &inst);
487
488 /** Remove all instructions that are not currently in the ROB.
489 * There's also an option to not squash delay slot instructions.*/
490 void removeInstsNotInROB(ThreadID tid);
491
492 /** Remove all instructions younger than the given sequence number. */
493 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
494
495 /** Removes the instruction pointed to by the iterator. */
496 inline void squashInstIt(const ListIt &instIt, ThreadID tid);
497
498 /** Cleans up all instructions on the remove list. */
499 void cleanUpRemovedInsts();
500
501 /** Debug function to print all instructions on the list. */
502 void dumpInsts();
503
504 public:
505#ifndef NDEBUG
506 /** Count of total number of dynamic instructions in flight. */
507 int instcount;
508#endif
509
510 /** List of all the instructions in flight. */
511 std::list<DynInstPtr> instList;
512
513 /** List of all the instructions that will be removed at the end of this
514 * cycle.
515 */
516 std::queue<ListIt> removeList;
517
518#ifdef DEBUG
519 /** Debug structure to keep track of the sequence numbers still in
520 * flight.
521 */
522 std::set<InstSeqNum> snList;
523#endif
524
525 /** Records if instructions need to be removed this cycle due to
526 * being retired or squashed.
527 */
528 bool removeInstsThisCycle;
529
530 protected:
531 /** The fetch stage. */
532 typename CPUPolicy::Fetch fetch;
533
534 /** The decode stage. */
535 typename CPUPolicy::Decode decode;
536
537 /** The dispatch stage. */
538 typename CPUPolicy::Rename rename;
539
540 /** The issue/execute/writeback stages. */
541 typename CPUPolicy::IEW iew;
542
543 /** The commit stage. */
544 typename CPUPolicy::Commit commit;
545
546 /** The register file. */
547 typename CPUPolicy::RegFile regFile;
548
549 /** The free list. */
550 typename CPUPolicy::FreeList freeList;
551
552 /** The rename map. */
553 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
554
555 /** The commit rename map. */
556 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
557
558 /** The re-order buffer. */
559 typename CPUPolicy::ROB rob;
560
561 /** Active Threads List */
562 std::list<ThreadID> activeThreads;
563
564 /** Integer Register Scoreboard */
565 Scoreboard scoreboard;
566
567 TheISA::ISA isa[Impl::MaxThreads];
568
| 197 class TickEvent : public Event
198 {
199 private:
200 /** Pointer to the CPU. */
201 FullO3CPU<Impl> *cpu;
202
203 public:
204 /** Constructs a tick event. */
205 TickEvent(FullO3CPU<Impl> *c);
206
207 /** Processes a tick event, calling tick() on the CPU. */
208 void process();
209 /** Returns the description of the tick event. */
210 const char *description() const;
211 };
212
213 /** The tick event used for scheduling CPU ticks. */
214 TickEvent tickEvent;
215
216 /** Schedule tick event, regardless of its current state. */
217 void scheduleTickEvent(int delay)
218 {
219 if (tickEvent.squashed())
220 reschedule(tickEvent, nextCycle(curTick() + ticks(delay)));
221 else if (!tickEvent.scheduled())
222 schedule(tickEvent, nextCycle(curTick() + ticks(delay)));
223 }
224
225 /** Unschedule tick event, regardless of its current state. */
226 void unscheduleTickEvent()
227 {
228 if (tickEvent.scheduled())
229 tickEvent.squash();
230 }
231
232 class ActivateThreadEvent : public Event
233 {
234 private:
235 /** Number of Thread to Activate */
236 ThreadID tid;
237
238 /** Pointer to the CPU. */
239 FullO3CPU<Impl> *cpu;
240
241 public:
242 /** Constructs the event. */
243 ActivateThreadEvent();
244
245 /** Initialize Event */
246 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
247
248 /** Processes the event, calling activateThread() on the CPU. */
249 void process();
250
251 /** Returns the description of the event. */
252 const char *description() const;
253 };
254
255 /** Schedule thread to activate , regardless of its current state. */
256 void
257 scheduleActivateThreadEvent(ThreadID tid, int delay)
258 {
259 // Schedule thread to activate, regardless of its current state.
260 if (activateThreadEvent[tid].squashed())
261 reschedule(activateThreadEvent[tid],
262 nextCycle(curTick() + ticks(delay)));
263 else if (!activateThreadEvent[tid].scheduled()) {
264 Tick when = nextCycle(curTick() + ticks(delay));
265
266 // Check if the deallocateEvent is also scheduled, and make
267 // sure they do not happen at same time causing a sleep that
268 // is never woken from.
269 if (deallocateContextEvent[tid].scheduled() &&
270 deallocateContextEvent[tid].when() == when) {
271 when++;
272 }
273
274 schedule(activateThreadEvent[tid], when);
275 }
276 }
277
278 /** Unschedule actiavte thread event, regardless of its current state. */
279 void
280 unscheduleActivateThreadEvent(ThreadID tid)
281 {
282 if (activateThreadEvent[tid].scheduled())
283 activateThreadEvent[tid].squash();
284 }
285
286 /** The tick event used for scheduling CPU ticks. */
287 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
288
289 class DeallocateContextEvent : public Event
290 {
291 private:
292 /** Number of Thread to deactivate */
293 ThreadID tid;
294
295 /** Should the thread be removed from the CPU? */
296 bool remove;
297
298 /** Pointer to the CPU. */
299 FullO3CPU<Impl> *cpu;
300
301 public:
302 /** Constructs the event. */
303 DeallocateContextEvent();
304
305 /** Initialize Event */
306 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
307
308 /** Processes the event, calling activateThread() on the CPU. */
309 void process();
310
311 /** Sets whether the thread should also be removed from the CPU. */
312 void setRemove(bool _remove) { remove = _remove; }
313
314 /** Returns the description of the event. */
315 const char *description() const;
316 };
317
318 /** Schedule cpu to deallocate thread context.*/
319 void
320 scheduleDeallocateContextEvent(ThreadID tid, bool remove, int delay)
321 {
322 // Schedule thread to activate, regardless of its current state.
323 if (deallocateContextEvent[tid].squashed())
324 reschedule(deallocateContextEvent[tid],
325 nextCycle(curTick() + ticks(delay)));
326 else if (!deallocateContextEvent[tid].scheduled())
327 schedule(deallocateContextEvent[tid],
328 nextCycle(curTick() + ticks(delay)));
329 }
330
331 /** Unschedule thread deallocation in CPU */
332 void
333 unscheduleDeallocateContextEvent(ThreadID tid)
334 {
335 if (deallocateContextEvent[tid].scheduled())
336 deallocateContextEvent[tid].squash();
337 }
338
339 /** The tick event used for scheduling CPU ticks. */
340 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
341
342 public:
343 /** Constructs a CPU with the given parameters. */
344 FullO3CPU(DerivO3CPUParams *params);
345 /** Destructor. */
346 ~FullO3CPU();
347
348 /** Registers statistics. */
349 void regStats();
350
351 void demapPage(Addr vaddr, uint64_t asn)
352 {
353 this->itb->demapPage(vaddr, asn);
354 this->dtb->demapPage(vaddr, asn);
355 }
356
357 void demapInstPage(Addr vaddr, uint64_t asn)
358 {
359 this->itb->demapPage(vaddr, asn);
360 }
361
362 void demapDataPage(Addr vaddr, uint64_t asn)
363 {
364 this->dtb->demapPage(vaddr, asn);
365 }
366
367 /** Returns a specific port. */
368 Port *getPort(const std::string &if_name, int idx);
369
370 /** Ticks CPU, calling tick() on each stage, and checking the overall
371 * activity to see if the CPU should deschedule itself.
372 */
373 void tick();
374
375 /** Initialize the CPU */
376 void init();
377
378 /** Returns the Number of Active Threads in the CPU */
379 int numActiveThreads()
380 { return activeThreads.size(); }
381
382 /** Add Thread to Active Threads List */
383 void activateThread(ThreadID tid);
384
385 /** Remove Thread from Active Threads List */
386 void deactivateThread(ThreadID tid);
387
388 /** Setup CPU to insert a thread's context */
389 void insertThread(ThreadID tid);
390
391 /** Remove all of a thread's context from CPU */
392 void removeThread(ThreadID tid);
393
394 /** Count the Total Instructions Committed in the CPU. */
395 virtual Counter totalInstructions() const;
396
397 /** Add Thread to Active Threads List. */
398 void activateContext(ThreadID tid, int delay);
399
400 /** Remove Thread from Active Threads List */
401 void suspendContext(ThreadID tid);
402
403 /** Remove Thread from Active Threads List &&
404 * Possibly Remove Thread Context from CPU.
405 */
406 bool deallocateContext(ThreadID tid, bool remove, int delay = 1);
407
408 /** Remove Thread from Active Threads List &&
409 * Remove Thread Context from CPU.
410 */
411 void haltContext(ThreadID tid);
412
413 /** Activate a Thread When CPU Resources are Available. */
414 void activateWhenReady(ThreadID tid);
415
416 /** Add or Remove a Thread Context in the CPU. */
417 void doContextSwitch();
418
419 /** Update The Order In Which We Process Threads. */
420 void updateThreadPriority();
421
422 /** Serialize state. */
423 virtual void serialize(std::ostream &os);
424
425 /** Unserialize from a checkpoint. */
426 virtual void unserialize(Checkpoint *cp, const std::string §ion);
427
428 public:
429#if !FULL_SYSTEM
430 /** Executes a syscall.
431 * @todo: Determine if this needs to be virtual.
432 */
433 void syscall(int64_t callnum, ThreadID tid);
434#endif
435
436 /** Starts draining the CPU's pipeline of all instructions in
437 * order to stop all memory accesses. */
438 virtual unsigned int drain(Event *drain_event);
439
440 /** Resumes execution after a drain. */
441 virtual void resume();
442
443 /** Signals to this CPU that a stage has completed switching out. */
444 void signalDrained();
445
446 /** Switches out this CPU. */
447 virtual void switchOut();
448
449 /** Takes over from another CPU. */
450 virtual void takeOverFrom(BaseCPU *oldCPU);
451
452 /** Get the current instruction sequence number, and increment it. */
453 InstSeqNum getAndIncrementInstSeq()
454 { return globalSeqNum++; }
455
456 /** Traps to handle given fault. */
457 void trap(Fault fault, ThreadID tid, StaticInstPtr inst);
458
459#if FULL_SYSTEM
460 /** HW return from error interrupt. */
461 Fault hwrei(ThreadID tid);
462
463 bool simPalCheck(int palFunc, ThreadID tid);
464
465 /** Returns the Fault for any valid interrupt. */
466 Fault getInterrupts();
467
468 /** Processes any an interrupt fault. */
469 void processInterrupts(Fault interrupt);
470
471 /** Halts the CPU. */
472 void halt() { panic("Halt not implemented!\n"); }
473
474 /** Check if this address is a valid instruction address. */
475 bool validInstAddr(Addr addr) { return true; }
476
477 /** Check if this address is a valid data address. */
478 bool validDataAddr(Addr addr) { return true; }
479#endif
480
481 /** Register accessors. Index refers to the physical register index. */
482
483 /** Reads a miscellaneous register. */
484 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
485
486 /** Reads a misc. register, including any side effects the read
487 * might have as defined by the architecture.
488 */
489 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
490
491 /** Sets a miscellaneous register. */
492 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
493 ThreadID tid);
494
495 /** Sets a misc. register, including any side effects the write
496 * might have as defined by the architecture.
497 */
498 void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
499 ThreadID tid);
500
501 uint64_t readIntReg(int reg_idx);
502
503 TheISA::FloatReg readFloatReg(int reg_idx);
504
505 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
506
507 void setIntReg(int reg_idx, uint64_t val);
508
509 void setFloatReg(int reg_idx, TheISA::FloatReg val);
510
511 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
512
513 uint64_t readArchIntReg(int reg_idx, ThreadID tid);
514
515 float readArchFloatReg(int reg_idx, ThreadID tid);
516
517 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
518
519 /** Architectural register accessors. Looks up in the commit
520 * rename table to obtain the true physical index of the
521 * architected register first, then accesses that physical
522 * register.
523 */
524 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
525
526 void setArchFloatReg(int reg_idx, float val, ThreadID tid);
527
528 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
529
530 /** Sets the commit PC state of a specific thread. */
531 void pcState(const TheISA::PCState &newPCState, ThreadID tid);
532
533 /** Reads the commit PC state of a specific thread. */
534 TheISA::PCState pcState(ThreadID tid);
535
536 /** Reads the commit PC of a specific thread. */
537 Addr instAddr(ThreadID tid);
538
539 /** Reads the commit micro PC of a specific thread. */
540 MicroPC microPC(ThreadID tid);
541
542 /** Reads the next PC of a specific thread. */
543 Addr nextInstAddr(ThreadID tid);
544
545 /** Initiates a squash of all in-flight instructions for a given
546 * thread. The source of the squash is an external update of
547 * state through the TC.
548 */
549 void squashFromTC(ThreadID tid);
550
551 /** Function to add instruction onto the head of the list of the
552 * instructions. Used when new instructions are fetched.
553 */
554 ListIt addInst(DynInstPtr &inst);
555
556 /** Function to tell the CPU that an instruction has completed. */
557 void instDone(ThreadID tid);
558
559 /** Remove an instruction from the front end of the list. There's
560 * no restriction on location of the instruction.
561 */
562 void removeFrontInst(DynInstPtr &inst);
563
564 /** Remove all instructions that are not currently in the ROB.
565 * There's also an option to not squash delay slot instructions.*/
566 void removeInstsNotInROB(ThreadID tid);
567
568 /** Remove all instructions younger than the given sequence number. */
569 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
570
571 /** Removes the instruction pointed to by the iterator. */
572 inline void squashInstIt(const ListIt &instIt, ThreadID tid);
573
574 /** Cleans up all instructions on the remove list. */
575 void cleanUpRemovedInsts();
576
577 /** Debug function to print all instructions on the list. */
578 void dumpInsts();
579
580 public:
581#ifndef NDEBUG
582 /** Count of total number of dynamic instructions in flight. */
583 int instcount;
584#endif
585
586 /** List of all the instructions in flight. */
587 std::list<DynInstPtr> instList;
588
589 /** List of all the instructions that will be removed at the end of this
590 * cycle.
591 */
592 std::queue<ListIt> removeList;
593
594#ifdef DEBUG
595 /** Debug structure to keep track of the sequence numbers still in
596 * flight.
597 */
598 std::set<InstSeqNum> snList;
599#endif
600
601 /** Records if instructions need to be removed this cycle due to
602 * being retired or squashed.
603 */
604 bool removeInstsThisCycle;
605
606 protected:
607 /** The fetch stage. */
608 typename CPUPolicy::Fetch fetch;
609
610 /** The decode stage. */
611 typename CPUPolicy::Decode decode;
612
613 /** The dispatch stage. */
614 typename CPUPolicy::Rename rename;
615
616 /** The issue/execute/writeback stages. */
617 typename CPUPolicy::IEW iew;
618
619 /** The commit stage. */
620 typename CPUPolicy::Commit commit;
621
622 /** The register file. */
623 typename CPUPolicy::RegFile regFile;
624
625 /** The free list. */
626 typename CPUPolicy::FreeList freeList;
627
628 /** The rename map. */
629 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
630
631 /** The commit rename map. */
632 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
633
634 /** The re-order buffer. */
635 typename CPUPolicy::ROB rob;
636
637 /** Active Threads List */
638 std::list<ThreadID> activeThreads;
639
640 /** Integer Register Scoreboard */
641 Scoreboard scoreboard;
642
643 TheISA::ISA isa[Impl::MaxThreads];
644
|
| 645 /** Instruction port. Note that it has to appear after the fetch stage. */
646 IcachePort icachePort;
647
648 /** Data port. Note that it has to appear after the iew stages */
649 DcachePort dcachePort;
650
|
569 public:
570 /** Enum to give each stage a specific index, so when calling
571 * activateStage() or deactivateStage(), they can specify which stage
572 * is being activated/deactivated.
573 */
574 enum StageIdx {
575 FetchIdx,
576 DecodeIdx,
577 RenameIdx,
578 IEWIdx,
579 CommitIdx,
580 NumStages };
581
582 /** Typedefs from the Impl to get the structs that each of the
583 * time buffers should use.
584 */
585 typedef typename CPUPolicy::TimeStruct TimeStruct;
586
587 typedef typename CPUPolicy::FetchStruct FetchStruct;
588
589 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
590
591 typedef typename CPUPolicy::RenameStruct RenameStruct;
592
593 typedef typename CPUPolicy::IEWStruct IEWStruct;
594
595 /** The main time buffer to do backwards communication. */
596 TimeBuffer<TimeStruct> timeBuffer;
597
598 /** The fetch stage's instruction queue. */
599 TimeBuffer<FetchStruct> fetchQueue;
600
601 /** The decode stage's instruction queue. */
602 TimeBuffer<DecodeStruct> decodeQueue;
603
604 /** The rename stage's instruction queue. */
605 TimeBuffer<RenameStruct> renameQueue;
606
607 /** The IEW stage's instruction queue. */
608 TimeBuffer<IEWStruct> iewQueue;
609
610 private:
611 /** The activity recorder; used to tell if the CPU has any
612 * activity remaining or if it can go to idle and deschedule
613 * itself.
614 */
615 ActivityRecorder activityRec;
616
617 public:
618 /** Records that there was time buffer activity this cycle. */
619 void activityThisCycle() { activityRec.activity(); }
620
621 /** Changes a stage's status to active within the activity recorder. */
622 void activateStage(const StageIdx idx)
623 { activityRec.activateStage(idx); }
624
625 /** Changes a stage's status to inactive within the activity recorder. */
626 void deactivateStage(const StageIdx idx)
627 { activityRec.deactivateStage(idx); }
628
629 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
630 void wakeCPU();
631
632#if FULL_SYSTEM
633 virtual void wakeup();
634#endif
635
636 /** Gets a free thread id. Use if thread ids change across system. */
637 ThreadID getFreeTid();
638
639 public:
640 /** Returns a pointer to a thread context. */
641 ThreadContext *
642 tcBase(ThreadID tid)
643 {
644 return thread[tid]->getTC();
645 }
646
647 /** The global sequence number counter. */
648 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
649
650#if USE_CHECKER
651 /** Pointer to the checker, which can dynamically verify
652 * instruction results at run time. This can be set to NULL if it
653 * is not being used.
654 */
655 Checker<DynInstPtr> *checker;
656#endif
657
658 /** Pointer to the system. */
659 System *system;
660
661 /** Event to call process() on once draining has completed. */
662 Event *drainEvent;
663
664 /** Counter of how many stages have completed draining. */
665 int drainCount;
666
667 /** Pointers to all of the threads in the CPU. */
668 std::vector<Thread *> thread;
669
670 /** Whether or not the CPU should defer its registration. */
671 bool deferRegistration;
672
673 /** Is there a context switch pending? */
674 bool contextSwitch;
675
676 /** Threads Scheduled to Enter CPU */
677 std::list<int> cpuWaitList;
678
679 /** The cycle that the CPU was last running, used for statistics. */
680 Tick lastRunningCycle;
681
682 /** The cycle that the CPU was last activated by a new thread*/
683 Tick lastActivatedCycle;
684
685 /** Mapping for system thread id to cpu id */
686 std::map<ThreadID, unsigned> threadMap;
687
688 /** Available thread ids in the cpu*/
689 std::vector<ThreadID> tids;
690
691 /** CPU read function, forwards read to LSQ. */
692 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
693 uint8_t *data, int load_idx)
694 {
695 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh,
696 data, load_idx);
697 }
698
699 /** CPU write function, forwards write to LSQ. */
700 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
701 uint8_t *data, int store_idx)
702 {
703 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
704 data, store_idx);
705 }
706
| 651 public:
652 /** Enum to give each stage a specific index, so when calling
653 * activateStage() or deactivateStage(), they can specify which stage
654 * is being activated/deactivated.
655 */
656 enum StageIdx {
657 FetchIdx,
658 DecodeIdx,
659 RenameIdx,
660 IEWIdx,
661 CommitIdx,
662 NumStages };
663
664 /** Typedefs from the Impl to get the structs that each of the
665 * time buffers should use.
666 */
667 typedef typename CPUPolicy::TimeStruct TimeStruct;
668
669 typedef typename CPUPolicy::FetchStruct FetchStruct;
670
671 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
672
673 typedef typename CPUPolicy::RenameStruct RenameStruct;
674
675 typedef typename CPUPolicy::IEWStruct IEWStruct;
676
677 /** The main time buffer to do backwards communication. */
678 TimeBuffer<TimeStruct> timeBuffer;
679
680 /** The fetch stage's instruction queue. */
681 TimeBuffer<FetchStruct> fetchQueue;
682
683 /** The decode stage's instruction queue. */
684 TimeBuffer<DecodeStruct> decodeQueue;
685
686 /** The rename stage's instruction queue. */
687 TimeBuffer<RenameStruct> renameQueue;
688
689 /** The IEW stage's instruction queue. */
690 TimeBuffer<IEWStruct> iewQueue;
691
692 private:
693 /** The activity recorder; used to tell if the CPU has any
694 * activity remaining or if it can go to idle and deschedule
695 * itself.
696 */
697 ActivityRecorder activityRec;
698
699 public:
700 /** Records that there was time buffer activity this cycle. */
701 void activityThisCycle() { activityRec.activity(); }
702
703 /** Changes a stage's status to active within the activity recorder. */
704 void activateStage(const StageIdx idx)
705 { activityRec.activateStage(idx); }
706
707 /** Changes a stage's status to inactive within the activity recorder. */
708 void deactivateStage(const StageIdx idx)
709 { activityRec.deactivateStage(idx); }
710
711 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
712 void wakeCPU();
713
714#if FULL_SYSTEM
715 virtual void wakeup();
716#endif
717
718 /** Gets a free thread id. Use if thread ids change across system. */
719 ThreadID getFreeTid();
720
721 public:
722 /** Returns a pointer to a thread context. */
723 ThreadContext *
724 tcBase(ThreadID tid)
725 {
726 return thread[tid]->getTC();
727 }
728
729 /** The global sequence number counter. */
730 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
731
732#if USE_CHECKER
733 /** Pointer to the checker, which can dynamically verify
734 * instruction results at run time. This can be set to NULL if it
735 * is not being used.
736 */
737 Checker<DynInstPtr> *checker;
738#endif
739
740 /** Pointer to the system. */
741 System *system;
742
743 /** Event to call process() on once draining has completed. */
744 Event *drainEvent;
745
746 /** Counter of how many stages have completed draining. */
747 int drainCount;
748
749 /** Pointers to all of the threads in the CPU. */
750 std::vector<Thread *> thread;
751
752 /** Whether or not the CPU should defer its registration. */
753 bool deferRegistration;
754
755 /** Is there a context switch pending? */
756 bool contextSwitch;
757
758 /** Threads Scheduled to Enter CPU */
759 std::list<int> cpuWaitList;
760
761 /** The cycle that the CPU was last running, used for statistics. */
762 Tick lastRunningCycle;
763
764 /** The cycle that the CPU was last activated by a new thread*/
765 Tick lastActivatedCycle;
766
767 /** Mapping for system thread id to cpu id */
768 std::map<ThreadID, unsigned> threadMap;
769
770 /** Available thread ids in the cpu*/
771 std::vector<ThreadID> tids;
772
773 /** CPU read function, forwards read to LSQ. */
774 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
775 uint8_t *data, int load_idx)
776 {
777 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh,
778 data, load_idx);
779 }
780
781 /** CPU write function, forwards write to LSQ. */
782 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
783 uint8_t *data, int store_idx)
784 {
785 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
786 data, store_idx);
787 }
788
|
| 789 /** Used by the fetch unit to get a hold of the instruction port. */
790 Port* getIcachePort() { return &icachePort; }
791
|
707 /** Get the dcache port (used to find block size for translations). */
| 792 /** Get the dcache port (used to find block size for translations). */
|
708 Port *getDcachePort() { return this->iew.ldstQueue.getDcachePort(); }
| 793 Port* getDcachePort() { return &dcachePort; }
|
709
710 Addr lockAddr;
711
712 /** Temporary fix for the lock flag, works in the UP case. */
713 bool lockFlag;
714
715 /** Stat for total number of times the CPU is descheduled. */
716 Stats::Scalar timesIdled;
717 /** Stat for total number of cycles the CPU spends descheduled. */
718 Stats::Scalar idleCycles;
719 /** Stat for total number of cycles the CPU spends descheduled due to a
720 * quiesce operation or waiting for an interrupt. */
721 Stats::Scalar quiesceCycles;
722 /** Stat for the number of committed instructions per thread. */
723 Stats::Vector committedInsts;
724 /** Stat for the total number of committed instructions. */
725 Stats::Scalar totalCommittedInsts;
726 /** Stat for the CPI per thread. */
727 Stats::Formula cpi;
728 /** Stat for the total CPI. */
729 Stats::Formula totalCpi;
730 /** Stat for the IPC per thread. */
731 Stats::Formula ipc;
732 /** Stat for the total IPC. */
733 Stats::Formula totalIpc;
734
735 //number of integer register file accesses
736 Stats::Scalar intRegfileReads;
737 Stats::Scalar intRegfileWrites;
738 //number of float register file accesses
739 Stats::Scalar fpRegfileReads;
740 Stats::Scalar fpRegfileWrites;
741 //number of misc
742 Stats::Scalar miscRegfileReads;
743 Stats::Scalar miscRegfileWrites;
744};
745
746#endif // __CPU_O3_CPU_HH__
| 794
795 Addr lockAddr;
796
797 /** Temporary fix for the lock flag, works in the UP case. */
798 bool lockFlag;
799
800 /** Stat for total number of times the CPU is descheduled. */
801 Stats::Scalar timesIdled;
802 /** Stat for total number of cycles the CPU spends descheduled. */
803 Stats::Scalar idleCycles;
804 /** Stat for total number of cycles the CPU spends descheduled due to a
805 * quiesce operation or waiting for an interrupt. */
806 Stats::Scalar quiesceCycles;
807 /** Stat for the number of committed instructions per thread. */
808 Stats::Vector committedInsts;
809 /** Stat for the total number of committed instructions. */
810 Stats::Scalar totalCommittedInsts;
811 /** Stat for the CPI per thread. */
812 Stats::Formula cpi;
813 /** Stat for the total CPI. */
814 Stats::Formula totalCpi;
815 /** Stat for the IPC per thread. */
816 Stats::Formula ipc;
817 /** Stat for the total IPC. */
818 Stats::Formula totalIpc;
819
820 //number of integer register file accesses
821 Stats::Scalar intRegfileReads;
822 Stats::Scalar intRegfileWrites;
823 //number of float register file accesses
824 Stats::Scalar fpRegfileReads;
825 Stats::Scalar fpRegfileWrites;
826 //number of misc
827 Stats::Scalar miscRegfileReads;
828 Stats::Scalar miscRegfileWrites;
829};
830
831#endif // __CPU_O3_CPU_HH__
|