cpu.hh (8229:78bf55f23338) cpu.hh (8460:3893d9d2c6c2)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * Copyright (c) 2011 Regents of the University of California
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Kevin Lim
30 * Korey Sewell
31 * Rick Strong
32 */
33
34#ifndef __CPU_O3_CPU_HH__
35#define __CPU_O3_CPU_HH__
36
37#include <iostream>
38#include <list>
39#include <queue>
40#include <set>
41#include <vector>
42
43#include "arch/types.hh"
44#include "base/statistics.hh"
45#include "config/full_system.hh"
46#include "config/the_isa.hh"
47#include "config/use_checker.hh"
48#include "cpu/o3/comm.hh"
49#include "cpu/o3/cpu_policy.hh"
50#include "cpu/o3/scoreboard.hh"
51#include "cpu/o3/thread_state.hh"
52#include "cpu/activity.hh"
53#include "cpu/base.hh"
54#include "cpu/simple_thread.hh"
55#include "cpu/timebuf.hh"
56//#include "cpu/o3/thread_context.hh"
57#include "params/DerivO3CPU.hh"
58#include "sim/process.hh"
59
60template <class>
61class Checker;
62class ThreadContext;
63template <class>
64class O3ThreadContext;
65
66class Checkpoint;
67class MemObject;
68class Process;
69
70class BaseCPUParams;
71
72class BaseO3CPU : public BaseCPU
73{
74 //Stuff that's pretty ISA independent will go here.
75 public:
76 BaseO3CPU(BaseCPUParams *params);
77
78 void regStats();
79};
80
81/**
82 * FullO3CPU class, has each of the stages (fetch through commit)
83 * within it, as well as all of the time buffers between stages. The
84 * tick() function for the CPU is defined here.
85 */
86template <class Impl>
87class FullO3CPU : public BaseO3CPU
88{
89 public:
90 // Typedefs from the Impl here.
91 typedef typename Impl::CPUPol CPUPolicy;
92 typedef typename Impl::DynInstPtr DynInstPtr;
93 typedef typename Impl::O3CPU O3CPU;
94
95 typedef O3ThreadState<Impl> ImplState;
96 typedef O3ThreadState<Impl> Thread;
97
98 typedef typename std::list<DynInstPtr>::iterator ListIt;
99
100 friend class O3ThreadContext<Impl>;
101
102 public:
103 enum Status {
104 Running,
105 Idle,
106 Halted,
107 Blocked,
108 SwitchedOut
109 };
110
111 TheISA::TLB * itb;
112 TheISA::TLB * dtb;
113
114 /** Overall CPU status. */
115 Status _status;
116
117 /** Per-thread status in CPU, used for SMT. */
118 Status _threadStatus[Impl::MaxThreads];
119
120 private:
121 class TickEvent : public Event
122 {
123 private:
124 /** Pointer to the CPU. */
125 FullO3CPU<Impl> *cpu;
126
127 public:
128 /** Constructs a tick event. */
129 TickEvent(FullO3CPU<Impl> *c);
130
131 /** Processes a tick event, calling tick() on the CPU. */
132 void process();
133 /** Returns the description of the tick event. */
134 const char *description() const;
135 };
136
137 /** The tick event used for scheduling CPU ticks. */
138 TickEvent tickEvent;
139
140 /** Schedule tick event, regardless of its current state. */
141 void scheduleTickEvent(int delay)
142 {
143 if (tickEvent.squashed())
144 reschedule(tickEvent, nextCycle(curTick() + ticks(delay)));
145 else if (!tickEvent.scheduled())
146 schedule(tickEvent, nextCycle(curTick() + ticks(delay)));
147 }
148
149 /** Unschedule tick event, regardless of its current state. */
150 void unscheduleTickEvent()
151 {
152 if (tickEvent.scheduled())
153 tickEvent.squash();
154 }
155
156 class ActivateThreadEvent : public Event
157 {
158 private:
159 /** Number of Thread to Activate */
160 ThreadID tid;
161
162 /** Pointer to the CPU. */
163 FullO3CPU<Impl> *cpu;
164
165 public:
166 /** Constructs the event. */
167 ActivateThreadEvent();
168
169 /** Initialize Event */
170 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
171
172 /** Processes the event, calling activateThread() on the CPU. */
173 void process();
174
175 /** Returns the description of the event. */
176 const char *description() const;
177 };
178
179 /** Schedule thread to activate , regardless of its current state. */
180 void
181 scheduleActivateThreadEvent(ThreadID tid, int delay)
182 {
183 // Schedule thread to activate, regardless of its current state.
184 if (activateThreadEvent[tid].squashed())
185 reschedule(activateThreadEvent[tid],
186 nextCycle(curTick() + ticks(delay)));
187 else if (!activateThreadEvent[tid].scheduled())
188 schedule(activateThreadEvent[tid],
189 nextCycle(curTick() + ticks(delay)));
190 }
191
192 /** Unschedule actiavte thread event, regardless of its current state. */
193 void
194 unscheduleActivateThreadEvent(ThreadID tid)
195 {
196 if (activateThreadEvent[tid].scheduled())
197 activateThreadEvent[tid].squash();
198 }
199
200 /** The tick event used for scheduling CPU ticks. */
201 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
202
203 class DeallocateContextEvent : public Event
204 {
205 private:
206 /** Number of Thread to deactivate */
207 ThreadID tid;
208
209 /** Should the thread be removed from the CPU? */
210 bool remove;
211
212 /** Pointer to the CPU. */
213 FullO3CPU<Impl> *cpu;
214
215 public:
216 /** Constructs the event. */
217 DeallocateContextEvent();
218
219 /** Initialize Event */
220 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
221
222 /** Processes the event, calling activateThread() on the CPU. */
223 void process();
224
225 /** Sets whether the thread should also be removed from the CPU. */
226 void setRemove(bool _remove) { remove = _remove; }
227
228 /** Returns the description of the event. */
229 const char *description() const;
230 };
231
232 /** Schedule cpu to deallocate thread context.*/
233 void
234 scheduleDeallocateContextEvent(ThreadID tid, bool remove, int delay)
235 {
236 // Schedule thread to activate, regardless of its current state.
237 if (deallocateContextEvent[tid].squashed())
238 reschedule(deallocateContextEvent[tid],
239 nextCycle(curTick() + ticks(delay)));
240 else if (!deallocateContextEvent[tid].scheduled())
241 schedule(deallocateContextEvent[tid],
242 nextCycle(curTick() + ticks(delay)));
243 }
244
245 /** Unschedule thread deallocation in CPU */
246 void
247 unscheduleDeallocateContextEvent(ThreadID tid)
248 {
249 if (deallocateContextEvent[tid].scheduled())
250 deallocateContextEvent[tid].squash();
251 }
252
253 /** The tick event used for scheduling CPU ticks. */
254 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
255
256 public:
257 /** Constructs a CPU with the given parameters. */
258 FullO3CPU(DerivO3CPUParams *params);
259 /** Destructor. */
260 ~FullO3CPU();
261
262 /** Registers statistics. */
263 void regStats();
264
265 void demapPage(Addr vaddr, uint64_t asn)
266 {
267 this->itb->demapPage(vaddr, asn);
268 this->dtb->demapPage(vaddr, asn);
269 }
270
271 void demapInstPage(Addr vaddr, uint64_t asn)
272 {
273 this->itb->demapPage(vaddr, asn);
274 }
275
276 void demapDataPage(Addr vaddr, uint64_t asn)
277 {
278 this->dtb->demapPage(vaddr, asn);
279 }
280
281 /** Returns a specific port. */
282 Port *getPort(const std::string &if_name, int idx);
283
284 /** Ticks CPU, calling tick() on each stage, and checking the overall
285 * activity to see if the CPU should deschedule itself.
286 */
287 void tick();
288
289 /** Initialize the CPU */
290 void init();
291
292 /** Returns the Number of Active Threads in the CPU */
293 int numActiveThreads()
294 { return activeThreads.size(); }
295
296 /** Add Thread to Active Threads List */
297 void activateThread(ThreadID tid);
298
299 /** Remove Thread from Active Threads List */
300 void deactivateThread(ThreadID tid);
301
302 /** Setup CPU to insert a thread's context */
303 void insertThread(ThreadID tid);
304
305 /** Remove all of a thread's context from CPU */
306 void removeThread(ThreadID tid);
307
308 /** Count the Total Instructions Committed in the CPU. */
309 virtual Counter totalInstructions() const;
310
311 /** Add Thread to Active Threads List. */
312 void activateContext(ThreadID tid, int delay);
313
314 /** Remove Thread from Active Threads List */
315 void suspendContext(ThreadID tid);
316
317 /** Remove Thread from Active Threads List &&
318 * Possibly Remove Thread Context from CPU.
319 */
320 bool deallocateContext(ThreadID tid, bool remove, int delay = 1);
321
322 /** Remove Thread from Active Threads List &&
323 * Remove Thread Context from CPU.
324 */
325 void haltContext(ThreadID tid);
326
327 /** Activate a Thread When CPU Resources are Available. */
328 void activateWhenReady(ThreadID tid);
329
330 /** Add or Remove a Thread Context in the CPU. */
331 void doContextSwitch();
332
333 /** Update The Order In Which We Process Threads. */
334 void updateThreadPriority();
335
336 /** Serialize state. */
337 virtual void serialize(std::ostream &os);
338
339 /** Unserialize from a checkpoint. */
340 virtual void unserialize(Checkpoint *cp, const std::string &section);
341
342 public:
343#if !FULL_SYSTEM
344 /** Executes a syscall.
345 * @todo: Determine if this needs to be virtual.
346 */
347 void syscall(int64_t callnum, ThreadID tid);
348#endif
349
350 /** Starts draining the CPU's pipeline of all instructions in
351 * order to stop all memory accesses. */
352 virtual unsigned int drain(Event *drain_event);
353
354 /** Resumes execution after a drain. */
355 virtual void resume();
356
357 /** Signals to this CPU that a stage has completed switching out. */
358 void signalDrained();
359
360 /** Switches out this CPU. */
361 virtual void switchOut();
362
363 /** Takes over from another CPU. */
364 virtual void takeOverFrom(BaseCPU *oldCPU);
365
366 /** Get the current instruction sequence number, and increment it. */
367 InstSeqNum getAndIncrementInstSeq()
368 { return globalSeqNum++; }
369
370 /** Traps to handle given fault. */
371 void trap(Fault fault, ThreadID tid, StaticInstPtr inst);
372
373#if FULL_SYSTEM
374 /** HW return from error interrupt. */
375 Fault hwrei(ThreadID tid);
376
377 bool simPalCheck(int palFunc, ThreadID tid);
378
379 /** Returns the Fault for any valid interrupt. */
380 Fault getInterrupts();
381
382 /** Processes any an interrupt fault. */
383 void processInterrupts(Fault interrupt);
384
385 /** Halts the CPU. */
386 void halt() { panic("Halt not implemented!\n"); }
387
388 /** Update the Virt and Phys ports of all ThreadContexts to
389 * reflect change in memory connections. */
390 void updateMemPorts();
391
392 /** Check if this address is a valid instruction address. */
393 bool validInstAddr(Addr addr) { return true; }
394
395 /** Check if this address is a valid data address. */
396 bool validDataAddr(Addr addr) { return true; }
397#endif
398
399 /** Register accessors. Index refers to the physical register index. */
400
401 /** Reads a miscellaneous register. */
402 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
403
404 /** Reads a misc. register, including any side effects the read
405 * might have as defined by the architecture.
406 */
407 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
408
409 /** Sets a miscellaneous register. */
410 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
411 ThreadID tid);
412
413 /** Sets a misc. register, including any side effects the write
414 * might have as defined by the architecture.
415 */
416 void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
417 ThreadID tid);
418
419 uint64_t readIntReg(int reg_idx);
420
421 TheISA::FloatReg readFloatReg(int reg_idx);
422
423 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
424
425 void setIntReg(int reg_idx, uint64_t val);
426
427 void setFloatReg(int reg_idx, TheISA::FloatReg val);
428
429 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
430
431 uint64_t readArchIntReg(int reg_idx, ThreadID tid);
432
433 float readArchFloatReg(int reg_idx, ThreadID tid);
434
435 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
436
437 /** Architectural register accessors. Looks up in the commit
438 * rename table to obtain the true physical index of the
439 * architected register first, then accesses that physical
440 * register.
441 */
442 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
443
444 void setArchFloatReg(int reg_idx, float val, ThreadID tid);
445
446 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
447
448 /** Sets the commit PC state of a specific thread. */
449 void pcState(const TheISA::PCState &newPCState, ThreadID tid);
450
451 /** Reads the commit PC state of a specific thread. */
452 TheISA::PCState pcState(ThreadID tid);
453
454 /** Reads the commit PC of a specific thread. */
455 Addr instAddr(ThreadID tid);
456
457 /** Reads the commit micro PC of a specific thread. */
458 MicroPC microPC(ThreadID tid);
459
460 /** Reads the next PC of a specific thread. */
461 Addr nextInstAddr(ThreadID tid);
462
463 /** Initiates a squash of all in-flight instructions for a given
464 * thread. The source of the squash is an external update of
465 * state through the TC.
466 */
467 void squashFromTC(ThreadID tid);
468
469 /** Function to add instruction onto the head of the list of the
470 * instructions. Used when new instructions are fetched.
471 */
472 ListIt addInst(DynInstPtr &inst);
473
474 /** Function to tell the CPU that an instruction has completed. */
475 void instDone(ThreadID tid);
476
477 /** Add Instructions to the CPU Remove List*/
478 void addToRemoveList(DynInstPtr &inst);
479
480 /** Remove an instruction from the front end of the list. There's
481 * no restriction on location of the instruction.
482 */
483 void removeFrontInst(DynInstPtr &inst);
484
485 /** Remove all instructions that are not currently in the ROB.
486 * There's also an option to not squash delay slot instructions.*/
487 void removeInstsNotInROB(ThreadID tid);
488
489 /** Remove all instructions younger than the given sequence number. */
490 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
491
492 /** Removes the instruction pointed to by the iterator. */
493 inline void squashInstIt(const ListIt &instIt, ThreadID tid);
494
495 /** Cleans up all instructions on the remove list. */
496 void cleanUpRemovedInsts();
497
498 /** Debug function to print all instructions on the list. */
499 void dumpInsts();
500
501 public:
502#ifndef NDEBUG
503 /** Count of total number of dynamic instructions in flight. */
504 int instcount;
505#endif
506
507 /** List of all the instructions in flight. */
508 std::list<DynInstPtr> instList;
509
510 /** List of all the instructions that will be removed at the end of this
511 * cycle.
512 */
513 std::queue<ListIt> removeList;
514
515#ifdef DEBUG
516 /** Debug structure to keep track of the sequence numbers still in
517 * flight.
518 */
519 std::set<InstSeqNum> snList;
520#endif
521
522 /** Records if instructions need to be removed this cycle due to
523 * being retired or squashed.
524 */
525 bool removeInstsThisCycle;
526
527 protected:
528 /** The fetch stage. */
529 typename CPUPolicy::Fetch fetch;
530
531 /** The decode stage. */
532 typename CPUPolicy::Decode decode;
533
534 /** The dispatch stage. */
535 typename CPUPolicy::Rename rename;
536
537 /** The issue/execute/writeback stages. */
538 typename CPUPolicy::IEW iew;
539
540 /** The commit stage. */
541 typename CPUPolicy::Commit commit;
542
543 /** The register file. */
544 typename CPUPolicy::RegFile regFile;
545
546 /** The free list. */
547 typename CPUPolicy::FreeList freeList;
548
549 /** The rename map. */
550 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
551
552 /** The commit rename map. */
553 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
554
555 /** The re-order buffer. */
556 typename CPUPolicy::ROB rob;
557
558 /** Active Threads List */
559 std::list<ThreadID> activeThreads;
560
561 /** Integer Register Scoreboard */
562 Scoreboard scoreboard;
563
564 TheISA::ISA isa[Impl::MaxThreads];
565
566 public:
567 /** Enum to give each stage a specific index, so when calling
568 * activateStage() or deactivateStage(), they can specify which stage
569 * is being activated/deactivated.
570 */
571 enum StageIdx {
572 FetchIdx,
573 DecodeIdx,
574 RenameIdx,
575 IEWIdx,
576 CommitIdx,
577 NumStages };
578
579 /** Typedefs from the Impl to get the structs that each of the
580 * time buffers should use.
581 */
582 typedef typename CPUPolicy::TimeStruct TimeStruct;
583
584 typedef typename CPUPolicy::FetchStruct FetchStruct;
585
586 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
587
588 typedef typename CPUPolicy::RenameStruct RenameStruct;
589
590 typedef typename CPUPolicy::IEWStruct IEWStruct;
591
592 /** The main time buffer to do backwards communication. */
593 TimeBuffer<TimeStruct> timeBuffer;
594
595 /** The fetch stage's instruction queue. */
596 TimeBuffer<FetchStruct> fetchQueue;
597
598 /** The decode stage's instruction queue. */
599 TimeBuffer<DecodeStruct> decodeQueue;
600
601 /** The rename stage's instruction queue. */
602 TimeBuffer<RenameStruct> renameQueue;
603
604 /** The IEW stage's instruction queue. */
605 TimeBuffer<IEWStruct> iewQueue;
606
607 private:
608 /** The activity recorder; used to tell if the CPU has any
609 * activity remaining or if it can go to idle and deschedule
610 * itself.
611 */
612 ActivityRecorder activityRec;
613
614 public:
615 /** Records that there was time buffer activity this cycle. */
616 void activityThisCycle() { activityRec.activity(); }
617
618 /** Changes a stage's status to active within the activity recorder. */
619 void activateStage(const StageIdx idx)
620 { activityRec.activateStage(idx); }
621
622 /** Changes a stage's status to inactive within the activity recorder. */
623 void deactivateStage(const StageIdx idx)
624 { activityRec.deactivateStage(idx); }
625
626 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
627 void wakeCPU();
628
629#if FULL_SYSTEM
630 virtual void wakeup();
631#endif
632
633 /** Gets a free thread id. Use if thread ids change across system. */
634 ThreadID getFreeTid();
635
636 public:
637 /** Returns a pointer to a thread context. */
638 ThreadContext *
639 tcBase(ThreadID tid)
640 {
641 return thread[tid]->getTC();
642 }
643
644 /** The global sequence number counter. */
645 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
646
647#if USE_CHECKER
648 /** Pointer to the checker, which can dynamically verify
649 * instruction results at run time. This can be set to NULL if it
650 * is not being used.
651 */
652 Checker<DynInstPtr> *checker;
653#endif
654
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * Copyright (c) 2011 Regents of the University of California
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Kevin Lim
30 * Korey Sewell
31 * Rick Strong
32 */
33
34#ifndef __CPU_O3_CPU_HH__
35#define __CPU_O3_CPU_HH__
36
37#include <iostream>
38#include <list>
39#include <queue>
40#include <set>
41#include <vector>
42
43#include "arch/types.hh"
44#include "base/statistics.hh"
45#include "config/full_system.hh"
46#include "config/the_isa.hh"
47#include "config/use_checker.hh"
48#include "cpu/o3/comm.hh"
49#include "cpu/o3/cpu_policy.hh"
50#include "cpu/o3/scoreboard.hh"
51#include "cpu/o3/thread_state.hh"
52#include "cpu/activity.hh"
53#include "cpu/base.hh"
54#include "cpu/simple_thread.hh"
55#include "cpu/timebuf.hh"
56//#include "cpu/o3/thread_context.hh"
57#include "params/DerivO3CPU.hh"
58#include "sim/process.hh"
59
60template <class>
61class Checker;
62class ThreadContext;
63template <class>
64class O3ThreadContext;
65
66class Checkpoint;
67class MemObject;
68class Process;
69
70class BaseCPUParams;
71
72class BaseO3CPU : public BaseCPU
73{
74 //Stuff that's pretty ISA independent will go here.
75 public:
76 BaseO3CPU(BaseCPUParams *params);
77
78 void regStats();
79};
80
81/**
82 * FullO3CPU class, has each of the stages (fetch through commit)
83 * within it, as well as all of the time buffers between stages. The
84 * tick() function for the CPU is defined here.
85 */
86template <class Impl>
87class FullO3CPU : public BaseO3CPU
88{
89 public:
90 // Typedefs from the Impl here.
91 typedef typename Impl::CPUPol CPUPolicy;
92 typedef typename Impl::DynInstPtr DynInstPtr;
93 typedef typename Impl::O3CPU O3CPU;
94
95 typedef O3ThreadState<Impl> ImplState;
96 typedef O3ThreadState<Impl> Thread;
97
98 typedef typename std::list<DynInstPtr>::iterator ListIt;
99
100 friend class O3ThreadContext<Impl>;
101
102 public:
103 enum Status {
104 Running,
105 Idle,
106 Halted,
107 Blocked,
108 SwitchedOut
109 };
110
111 TheISA::TLB * itb;
112 TheISA::TLB * dtb;
113
114 /** Overall CPU status. */
115 Status _status;
116
117 /** Per-thread status in CPU, used for SMT. */
118 Status _threadStatus[Impl::MaxThreads];
119
120 private:
121 class TickEvent : public Event
122 {
123 private:
124 /** Pointer to the CPU. */
125 FullO3CPU<Impl> *cpu;
126
127 public:
128 /** Constructs a tick event. */
129 TickEvent(FullO3CPU<Impl> *c);
130
131 /** Processes a tick event, calling tick() on the CPU. */
132 void process();
133 /** Returns the description of the tick event. */
134 const char *description() const;
135 };
136
137 /** The tick event used for scheduling CPU ticks. */
138 TickEvent tickEvent;
139
140 /** Schedule tick event, regardless of its current state. */
141 void scheduleTickEvent(int delay)
142 {
143 if (tickEvent.squashed())
144 reschedule(tickEvent, nextCycle(curTick() + ticks(delay)));
145 else if (!tickEvent.scheduled())
146 schedule(tickEvent, nextCycle(curTick() + ticks(delay)));
147 }
148
149 /** Unschedule tick event, regardless of its current state. */
150 void unscheduleTickEvent()
151 {
152 if (tickEvent.scheduled())
153 tickEvent.squash();
154 }
155
156 class ActivateThreadEvent : public Event
157 {
158 private:
159 /** Number of Thread to Activate */
160 ThreadID tid;
161
162 /** Pointer to the CPU. */
163 FullO3CPU<Impl> *cpu;
164
165 public:
166 /** Constructs the event. */
167 ActivateThreadEvent();
168
169 /** Initialize Event */
170 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
171
172 /** Processes the event, calling activateThread() on the CPU. */
173 void process();
174
175 /** Returns the description of the event. */
176 const char *description() const;
177 };
178
179 /** Schedule thread to activate , regardless of its current state. */
180 void
181 scheduleActivateThreadEvent(ThreadID tid, int delay)
182 {
183 // Schedule thread to activate, regardless of its current state.
184 if (activateThreadEvent[tid].squashed())
185 reschedule(activateThreadEvent[tid],
186 nextCycle(curTick() + ticks(delay)));
187 else if (!activateThreadEvent[tid].scheduled())
188 schedule(activateThreadEvent[tid],
189 nextCycle(curTick() + ticks(delay)));
190 }
191
192 /** Unschedule actiavte thread event, regardless of its current state. */
193 void
194 unscheduleActivateThreadEvent(ThreadID tid)
195 {
196 if (activateThreadEvent[tid].scheduled())
197 activateThreadEvent[tid].squash();
198 }
199
200 /** The tick event used for scheduling CPU ticks. */
201 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
202
203 class DeallocateContextEvent : public Event
204 {
205 private:
206 /** Number of Thread to deactivate */
207 ThreadID tid;
208
209 /** Should the thread be removed from the CPU? */
210 bool remove;
211
212 /** Pointer to the CPU. */
213 FullO3CPU<Impl> *cpu;
214
215 public:
216 /** Constructs the event. */
217 DeallocateContextEvent();
218
219 /** Initialize Event */
220 void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
221
222 /** Processes the event, calling activateThread() on the CPU. */
223 void process();
224
225 /** Sets whether the thread should also be removed from the CPU. */
226 void setRemove(bool _remove) { remove = _remove; }
227
228 /** Returns the description of the event. */
229 const char *description() const;
230 };
231
232 /** Schedule cpu to deallocate thread context.*/
233 void
234 scheduleDeallocateContextEvent(ThreadID tid, bool remove, int delay)
235 {
236 // Schedule thread to activate, regardless of its current state.
237 if (deallocateContextEvent[tid].squashed())
238 reschedule(deallocateContextEvent[tid],
239 nextCycle(curTick() + ticks(delay)));
240 else if (!deallocateContextEvent[tid].scheduled())
241 schedule(deallocateContextEvent[tid],
242 nextCycle(curTick() + ticks(delay)));
243 }
244
245 /** Unschedule thread deallocation in CPU */
246 void
247 unscheduleDeallocateContextEvent(ThreadID tid)
248 {
249 if (deallocateContextEvent[tid].scheduled())
250 deallocateContextEvent[tid].squash();
251 }
252
253 /** The tick event used for scheduling CPU ticks. */
254 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
255
256 public:
257 /** Constructs a CPU with the given parameters. */
258 FullO3CPU(DerivO3CPUParams *params);
259 /** Destructor. */
260 ~FullO3CPU();
261
262 /** Registers statistics. */
263 void regStats();
264
265 void demapPage(Addr vaddr, uint64_t asn)
266 {
267 this->itb->demapPage(vaddr, asn);
268 this->dtb->demapPage(vaddr, asn);
269 }
270
271 void demapInstPage(Addr vaddr, uint64_t asn)
272 {
273 this->itb->demapPage(vaddr, asn);
274 }
275
276 void demapDataPage(Addr vaddr, uint64_t asn)
277 {
278 this->dtb->demapPage(vaddr, asn);
279 }
280
281 /** Returns a specific port. */
282 Port *getPort(const std::string &if_name, int idx);
283
284 /** Ticks CPU, calling tick() on each stage, and checking the overall
285 * activity to see if the CPU should deschedule itself.
286 */
287 void tick();
288
289 /** Initialize the CPU */
290 void init();
291
292 /** Returns the Number of Active Threads in the CPU */
293 int numActiveThreads()
294 { return activeThreads.size(); }
295
296 /** Add Thread to Active Threads List */
297 void activateThread(ThreadID tid);
298
299 /** Remove Thread from Active Threads List */
300 void deactivateThread(ThreadID tid);
301
302 /** Setup CPU to insert a thread's context */
303 void insertThread(ThreadID tid);
304
305 /** Remove all of a thread's context from CPU */
306 void removeThread(ThreadID tid);
307
308 /** Count the Total Instructions Committed in the CPU. */
309 virtual Counter totalInstructions() const;
310
311 /** Add Thread to Active Threads List. */
312 void activateContext(ThreadID tid, int delay);
313
314 /** Remove Thread from Active Threads List */
315 void suspendContext(ThreadID tid);
316
317 /** Remove Thread from Active Threads List &&
318 * Possibly Remove Thread Context from CPU.
319 */
320 bool deallocateContext(ThreadID tid, bool remove, int delay = 1);
321
322 /** Remove Thread from Active Threads List &&
323 * Remove Thread Context from CPU.
324 */
325 void haltContext(ThreadID tid);
326
327 /** Activate a Thread When CPU Resources are Available. */
328 void activateWhenReady(ThreadID tid);
329
330 /** Add or Remove a Thread Context in the CPU. */
331 void doContextSwitch();
332
333 /** Update The Order In Which We Process Threads. */
334 void updateThreadPriority();
335
336 /** Serialize state. */
337 virtual void serialize(std::ostream &os);
338
339 /** Unserialize from a checkpoint. */
340 virtual void unserialize(Checkpoint *cp, const std::string &section);
341
342 public:
343#if !FULL_SYSTEM
344 /** Executes a syscall.
345 * @todo: Determine if this needs to be virtual.
346 */
347 void syscall(int64_t callnum, ThreadID tid);
348#endif
349
350 /** Starts draining the CPU's pipeline of all instructions in
351 * order to stop all memory accesses. */
352 virtual unsigned int drain(Event *drain_event);
353
354 /** Resumes execution after a drain. */
355 virtual void resume();
356
357 /** Signals to this CPU that a stage has completed switching out. */
358 void signalDrained();
359
360 /** Switches out this CPU. */
361 virtual void switchOut();
362
363 /** Takes over from another CPU. */
364 virtual void takeOverFrom(BaseCPU *oldCPU);
365
366 /** Get the current instruction sequence number, and increment it. */
367 InstSeqNum getAndIncrementInstSeq()
368 { return globalSeqNum++; }
369
370 /** Traps to handle given fault. */
371 void trap(Fault fault, ThreadID tid, StaticInstPtr inst);
372
373#if FULL_SYSTEM
374 /** HW return from error interrupt. */
375 Fault hwrei(ThreadID tid);
376
377 bool simPalCheck(int palFunc, ThreadID tid);
378
379 /** Returns the Fault for any valid interrupt. */
380 Fault getInterrupts();
381
382 /** Processes any an interrupt fault. */
383 void processInterrupts(Fault interrupt);
384
385 /** Halts the CPU. */
386 void halt() { panic("Halt not implemented!\n"); }
387
388 /** Update the Virt and Phys ports of all ThreadContexts to
389 * reflect change in memory connections. */
390 void updateMemPorts();
391
392 /** Check if this address is a valid instruction address. */
393 bool validInstAddr(Addr addr) { return true; }
394
395 /** Check if this address is a valid data address. */
396 bool validDataAddr(Addr addr) { return true; }
397#endif
398
399 /** Register accessors. Index refers to the physical register index. */
400
401 /** Reads a miscellaneous register. */
402 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
403
404 /** Reads a misc. register, including any side effects the read
405 * might have as defined by the architecture.
406 */
407 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
408
409 /** Sets a miscellaneous register. */
410 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
411 ThreadID tid);
412
413 /** Sets a misc. register, including any side effects the write
414 * might have as defined by the architecture.
415 */
416 void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
417 ThreadID tid);
418
419 uint64_t readIntReg(int reg_idx);
420
421 TheISA::FloatReg readFloatReg(int reg_idx);
422
423 TheISA::FloatRegBits readFloatRegBits(int reg_idx);
424
425 void setIntReg(int reg_idx, uint64_t val);
426
427 void setFloatReg(int reg_idx, TheISA::FloatReg val);
428
429 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
430
431 uint64_t readArchIntReg(int reg_idx, ThreadID tid);
432
433 float readArchFloatReg(int reg_idx, ThreadID tid);
434
435 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
436
437 /** Architectural register accessors. Looks up in the commit
438 * rename table to obtain the true physical index of the
439 * architected register first, then accesses that physical
440 * register.
441 */
442 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
443
444 void setArchFloatReg(int reg_idx, float val, ThreadID tid);
445
446 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
447
448 /** Sets the commit PC state of a specific thread. */
449 void pcState(const TheISA::PCState &newPCState, ThreadID tid);
450
451 /** Reads the commit PC state of a specific thread. */
452 TheISA::PCState pcState(ThreadID tid);
453
454 /** Reads the commit PC of a specific thread. */
455 Addr instAddr(ThreadID tid);
456
457 /** Reads the commit micro PC of a specific thread. */
458 MicroPC microPC(ThreadID tid);
459
460 /** Reads the next PC of a specific thread. */
461 Addr nextInstAddr(ThreadID tid);
462
463 /** Initiates a squash of all in-flight instructions for a given
464 * thread. The source of the squash is an external update of
465 * state through the TC.
466 */
467 void squashFromTC(ThreadID tid);
468
469 /** Function to add instruction onto the head of the list of the
470 * instructions. Used when new instructions are fetched.
471 */
472 ListIt addInst(DynInstPtr &inst);
473
474 /** Function to tell the CPU that an instruction has completed. */
475 void instDone(ThreadID tid);
476
477 /** Add Instructions to the CPU Remove List*/
478 void addToRemoveList(DynInstPtr &inst);
479
480 /** Remove an instruction from the front end of the list. There's
481 * no restriction on location of the instruction.
482 */
483 void removeFrontInst(DynInstPtr &inst);
484
485 /** Remove all instructions that are not currently in the ROB.
486 * There's also an option to not squash delay slot instructions.*/
487 void removeInstsNotInROB(ThreadID tid);
488
489 /** Remove all instructions younger than the given sequence number. */
490 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
491
492 /** Removes the instruction pointed to by the iterator. */
493 inline void squashInstIt(const ListIt &instIt, ThreadID tid);
494
495 /** Cleans up all instructions on the remove list. */
496 void cleanUpRemovedInsts();
497
498 /** Debug function to print all instructions on the list. */
499 void dumpInsts();
500
501 public:
502#ifndef NDEBUG
503 /** Count of total number of dynamic instructions in flight. */
504 int instcount;
505#endif
506
507 /** List of all the instructions in flight. */
508 std::list<DynInstPtr> instList;
509
510 /** List of all the instructions that will be removed at the end of this
511 * cycle.
512 */
513 std::queue<ListIt> removeList;
514
515#ifdef DEBUG
516 /** Debug structure to keep track of the sequence numbers still in
517 * flight.
518 */
519 std::set<InstSeqNum> snList;
520#endif
521
522 /** Records if instructions need to be removed this cycle due to
523 * being retired or squashed.
524 */
525 bool removeInstsThisCycle;
526
527 protected:
528 /** The fetch stage. */
529 typename CPUPolicy::Fetch fetch;
530
531 /** The decode stage. */
532 typename CPUPolicy::Decode decode;
533
534 /** The dispatch stage. */
535 typename CPUPolicy::Rename rename;
536
537 /** The issue/execute/writeback stages. */
538 typename CPUPolicy::IEW iew;
539
540 /** The commit stage. */
541 typename CPUPolicy::Commit commit;
542
543 /** The register file. */
544 typename CPUPolicy::RegFile regFile;
545
546 /** The free list. */
547 typename CPUPolicy::FreeList freeList;
548
549 /** The rename map. */
550 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
551
552 /** The commit rename map. */
553 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
554
555 /** The re-order buffer. */
556 typename CPUPolicy::ROB rob;
557
558 /** Active Threads List */
559 std::list<ThreadID> activeThreads;
560
561 /** Integer Register Scoreboard */
562 Scoreboard scoreboard;
563
564 TheISA::ISA isa[Impl::MaxThreads];
565
566 public:
567 /** Enum to give each stage a specific index, so when calling
568 * activateStage() or deactivateStage(), they can specify which stage
569 * is being activated/deactivated.
570 */
571 enum StageIdx {
572 FetchIdx,
573 DecodeIdx,
574 RenameIdx,
575 IEWIdx,
576 CommitIdx,
577 NumStages };
578
579 /** Typedefs from the Impl to get the structs that each of the
580 * time buffers should use.
581 */
582 typedef typename CPUPolicy::TimeStruct TimeStruct;
583
584 typedef typename CPUPolicy::FetchStruct FetchStruct;
585
586 typedef typename CPUPolicy::DecodeStruct DecodeStruct;
587
588 typedef typename CPUPolicy::RenameStruct RenameStruct;
589
590 typedef typename CPUPolicy::IEWStruct IEWStruct;
591
592 /** The main time buffer to do backwards communication. */
593 TimeBuffer<TimeStruct> timeBuffer;
594
595 /** The fetch stage's instruction queue. */
596 TimeBuffer<FetchStruct> fetchQueue;
597
598 /** The decode stage's instruction queue. */
599 TimeBuffer<DecodeStruct> decodeQueue;
600
601 /** The rename stage's instruction queue. */
602 TimeBuffer<RenameStruct> renameQueue;
603
604 /** The IEW stage's instruction queue. */
605 TimeBuffer<IEWStruct> iewQueue;
606
607 private:
608 /** The activity recorder; used to tell if the CPU has any
609 * activity remaining or if it can go to idle and deschedule
610 * itself.
611 */
612 ActivityRecorder activityRec;
613
614 public:
615 /** Records that there was time buffer activity this cycle. */
616 void activityThisCycle() { activityRec.activity(); }
617
618 /** Changes a stage's status to active within the activity recorder. */
619 void activateStage(const StageIdx idx)
620 { activityRec.activateStage(idx); }
621
622 /** Changes a stage's status to inactive within the activity recorder. */
623 void deactivateStage(const StageIdx idx)
624 { activityRec.deactivateStage(idx); }
625
626 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
627 void wakeCPU();
628
629#if FULL_SYSTEM
630 virtual void wakeup();
631#endif
632
633 /** Gets a free thread id. Use if thread ids change across system. */
634 ThreadID getFreeTid();
635
636 public:
637 /** Returns a pointer to a thread context. */
638 ThreadContext *
639 tcBase(ThreadID tid)
640 {
641 return thread[tid]->getTC();
642 }
643
644 /** The global sequence number counter. */
645 InstSeqNum globalSeqNum;//[Impl::MaxThreads];
646
647#if USE_CHECKER
648 /** Pointer to the checker, which can dynamically verify
649 * instruction results at run time. This can be set to NULL if it
650 * is not being used.
651 */
652 Checker<DynInstPtr> *checker;
653#endif
654
655#if FULL_SYSTEM
656 /** Pointer to the system. */
657 System *system;
655 /** Pointer to the system. */
656 System *system;
658#endif
659
660 /** Event to call process() on once draining has completed. */
661 Event *drainEvent;
662
663 /** Counter of how many stages have completed draining. */
664 int drainCount;
665
666 /** Pointers to all of the threads in the CPU. */
667 std::vector<Thread *> thread;
668
669 /** Whether or not the CPU should defer its registration. */
670 bool deferRegistration;
671
672 /** Is there a context switch pending? */
673 bool contextSwitch;
674
675 /** Threads Scheduled to Enter CPU */
676 std::list<int> cpuWaitList;
677
678 /** The cycle that the CPU was last running, used for statistics. */
679 Tick lastRunningCycle;
680
681 /** The cycle that the CPU was last activated by a new thread*/
682 Tick lastActivatedCycle;
683
684 /** Mapping for system thread id to cpu id */
685 std::map<ThreadID, unsigned> threadMap;
686
687 /** Available thread ids in the cpu*/
688 std::vector<ThreadID> tids;
689
690 /** CPU read function, forwards read to LSQ. */
691 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
692 uint8_t *data, int load_idx)
693 {
694 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh,
695 data, load_idx);
696 }
697
698 /** CPU write function, forwards write to LSQ. */
699 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
700 uint8_t *data, int store_idx)
701 {
702 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
703 data, store_idx);
704 }
705
706 /** Get the dcache port (used to find block size for translations). */
707 Port *getDcachePort() { return this->iew.ldstQueue.getDcachePort(); }
708
709 Addr lockAddr;
710
711 /** Temporary fix for the lock flag, works in the UP case. */
712 bool lockFlag;
713
714 /** Stat for total number of times the CPU is descheduled. */
715 Stats::Scalar timesIdled;
716 /** Stat for total number of cycles the CPU spends descheduled. */
717 Stats::Scalar idleCycles;
718 /** Stat for the number of committed instructions per thread. */
719 Stats::Vector committedInsts;
720 /** Stat for the total number of committed instructions. */
721 Stats::Scalar totalCommittedInsts;
722 /** Stat for the CPI per thread. */
723 Stats::Formula cpi;
724 /** Stat for the total CPI. */
725 Stats::Formula totalCpi;
726 /** Stat for the IPC per thread. */
727 Stats::Formula ipc;
728 /** Stat for the total IPC. */
729 Stats::Formula totalIpc;
730
731 //number of integer register file accesses
732 Stats::Scalar intRegfileReads;
733 Stats::Scalar intRegfileWrites;
734 //number of float register file accesses
735 Stats::Scalar fpRegfileReads;
736 Stats::Scalar fpRegfileWrites;
737 //number of misc
738 Stats::Scalar miscRegfileReads;
739 Stats::Scalar miscRegfileWrites;
740};
741
742#endif // __CPU_O3_CPU_HH__
657
658 /** Event to call process() on once draining has completed. */
659 Event *drainEvent;
660
661 /** Counter of how many stages have completed draining. */
662 int drainCount;
663
664 /** Pointers to all of the threads in the CPU. */
665 std::vector<Thread *> thread;
666
667 /** Whether or not the CPU should defer its registration. */
668 bool deferRegistration;
669
670 /** Is there a context switch pending? */
671 bool contextSwitch;
672
673 /** Threads Scheduled to Enter CPU */
674 std::list<int> cpuWaitList;
675
676 /** The cycle that the CPU was last running, used for statistics. */
677 Tick lastRunningCycle;
678
679 /** The cycle that the CPU was last activated by a new thread*/
680 Tick lastActivatedCycle;
681
682 /** Mapping for system thread id to cpu id */
683 std::map<ThreadID, unsigned> threadMap;
684
685 /** Available thread ids in the cpu*/
686 std::vector<ThreadID> tids;
687
688 /** CPU read function, forwards read to LSQ. */
689 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
690 uint8_t *data, int load_idx)
691 {
692 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh,
693 data, load_idx);
694 }
695
696 /** CPU write function, forwards write to LSQ. */
697 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
698 uint8_t *data, int store_idx)
699 {
700 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
701 data, store_idx);
702 }
703
704 /** Get the dcache port (used to find block size for translations). */
705 Port *getDcachePort() { return this->iew.ldstQueue.getDcachePort(); }
706
707 Addr lockAddr;
708
709 /** Temporary fix for the lock flag, works in the UP case. */
710 bool lockFlag;
711
712 /** Stat for total number of times the CPU is descheduled. */
713 Stats::Scalar timesIdled;
714 /** Stat for total number of cycles the CPU spends descheduled. */
715 Stats::Scalar idleCycles;
716 /** Stat for the number of committed instructions per thread. */
717 Stats::Vector committedInsts;
718 /** Stat for the total number of committed instructions. */
719 Stats::Scalar totalCommittedInsts;
720 /** Stat for the CPI per thread. */
721 Stats::Formula cpi;
722 /** Stat for the total CPI. */
723 Stats::Formula totalCpi;
724 /** Stat for the IPC per thread. */
725 Stats::Formula ipc;
726 /** Stat for the total IPC. */
727 Stats::Formula totalIpc;
728
729 //number of integer register file accesses
730 Stats::Scalar intRegfileReads;
731 Stats::Scalar intRegfileWrites;
732 //number of float register file accesses
733 Stats::Scalar fpRegfileReads;
734 Stats::Scalar fpRegfileWrites;
735 //number of misc
736 Stats::Scalar miscRegfileReads;
737 Stats::Scalar miscRegfileWrites;
738};
739
740#endif // __CPU_O3_CPU_HH__